| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/ |
| A D | hikey_pm.c | 37 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on()
39 curr_cluster = MPIDR_AFFLVL1_VAL(read_mpidr()); in hikey_pwr_domain_on()
56 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_on_finish()
65 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_on_finish()
82 cluster = MPIDR_AFFLVL1_VAL(mpidr); in hikey_pwr_domain_off()
90 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_off()
121 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_suspend()
149 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in hikey_pwr_domain_suspend_finish()
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| /arm-trusted-firmware-2.8.0/drivers/nxp/interconnect/ |
| A D | ls_ccn.c | 18 ccn_enter_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
30 ccn_exit_snoop_dvm_domain(1ULL << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
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| A D | ls_cci.c | 25 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_enter_coherency()
37 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_ls_interconnect_exit_coherency()
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| /arm-trusted-firmware-2.8.0/plat/socionext/synquacer/ |
| A D | sq_ccn.c | 36 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_enter_coherency()
44 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_sq_interconnect_exit_coherency()
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| /arm-trusted-firmware-2.8.0/plat/brcm/common/ |
| A D | brcm_ccn.c | 30 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_enter_coherency()
35 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_brcm_interconnect_exit_coherency()
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| /arm-trusted-firmware-2.8.0/plat/marvell/armada/common/ |
| A D | marvell_cci.c | 42 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_enter_coherency()
51 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_marvell_interconnect_exit_coherency()
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| A D | marvell_topology.c | 56 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in marvell_check_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/arm/common/ |
| A D | arm_cci.c | 41 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
49 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
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| A D | arm_ccn.c | 48 ccn_enter_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_enter_coherency()
56 ccn_exit_snoop_dvm_domain(1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in plat_arm_interconnect_exit_coherency()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8qm/ |
| A D | imx8qm_psci.c | 77 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_on()
108 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_pwr_domain_on_finish()
117 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_pwr_domain_off()
136 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_domain_suspend()
154 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend()
167 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend()
212 unsigned int cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in imx_domain_suspend_finish()
251 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()
263 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(mpidr)); in imx_domain_suspend_finish()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/aarch64/ |
| A D | platform_common.c | 78 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
85 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /arm-trusted-firmware-2.8.0/plat/socionext/uniphier/ |
| A D | uniphier_cci.c | 27 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_enable()
32 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in __uniphier_cci_disable()
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/aarch64/ |
| A D | platform_common.c | 83 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
88 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/ |
| A D | fvp_topology.c | 94 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
99 clus_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/renesas/common/ |
| A D | bl31_plat_setup.c | 59 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_enable()
64 cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr())); in plat_cci_disable()
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| /arm-trusted-firmware-2.8.0/plat/brcm/board/stingray/src/ |
| A D | brcm_pm_ops.c | 77 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_pwr_domain_on_finish()
105 switch (MPIDR_AFFLVL1_VAL(mpidr)) { in brcm_power_down_common()
123 ERROR("Invalid cluster #%" PRIx64 "\n", MPIDR_AFFLVL1_VAL(mpidr)); in brcm_power_down_common()
172 unsigned long cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr_el1()); in brcm_pwr_domain_off()
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| /arm-trusted-firmware-2.8.0/plat/qti/msm8916/ |
| A D | msm8916_topology.c | 24 MPIDR_AFFLVL1_VAL(mpidr) > 0 || in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | sunxi_topology.c | 23 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
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| A D | sunxi_cpu_ops.c | 51 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_off()
69 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in sunxi_cpu_on()
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| /arm-trusted-firmware-2.8.0/plat/imx/common/ |
| A D | imx8_topology.c | 32 cluster_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/xilinx/versal_net/ |
| A D | plat_topology.c | 48 cpu_id = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/ti/k3/common/ |
| A D | k3_topology.c | 28 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/drivers/nxp/pmu/ |
| A D | pmu.c | 26 | (1 << MPIDR_AFFLVL1_VAL(read_mpidr_el1())); in enable_timer_base_to_cluster()
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| /arm-trusted-firmware-2.8.0/plat/arm/board/arm_fpga/ |
| A D | fpga_topology.c | 62 (MPIDR_AFFLVL1_VAL(mpidr) >= FPGA_MAX_CPUS_PER_CLUSTER) || in plat_core_pos_by_mpidr()
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| /arm-trusted-firmware-2.8.0/plat/brcm/board/common/ |
| A D | timer_sync.c | 69 cluster_id = MPIDR_AFFLVL1_VAL(read_mpidr()); in brcm_timer_sync_init()
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