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Searched refs:MTK_WDT_BASE (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/include/
A Dplatform_def.h162 #define MTK_WDT_BASE (IO_PHYS + 0x00007000) macro
164 #define MTK_WDT_MODE (MTK_WDT_BASE + 0x0000)
165 #define MTK_WDT_LENGTH (MTK_WDT_BASE + 0x0004)
166 #define MTK_WDT_RESTART (MTK_WDT_BASE + 0x0008)
167 #define MTK_WDT_STATUS (MTK_WDT_BASE + 0x000C)
168 #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x0010)
169 #define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014)
170 #define MTK_WDT_SWSYSRST (MTK_WDT_BASE + 0x0018)
171 #define MTK_WDT_NONRST_REG (MTK_WDT_BASE + 0x0020)
172 #define MTK_WDT_NONRST_REG2 (MTK_WDT_BASE + 0x0024)
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/dfd/mt8188/
A Dplat_dfd.h22 #define MTK_WDT_BASE (RGU_BASE) macro
23 #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10)
24 #define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/dfd/
A Dplat_dfd.h25 #define MTK_WDT_BASE (RGU_BASE) macro
26 #define MTK_WDT_INTERVAL (MTK_WDT_BASE + 0x10)
27 #define MTK_WDT_LATCH_CTL2 (MTK_WDT_BASE + 0x48)

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