1 /* 2 * Copyright (C) 2018-2021 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 #ifndef A3700_PLAT_DEF_H 9 #define A3700_PLAT_DEF_H 10 11 #include <marvell_def.h> 12 13 14 #define MVEBU_MAX_CPUS_PER_CLUSTER 2 15 16 #define MVEBU_PRIMARY_CPU 0x0 17 18 /* 19 * The counter on A3700 is always fed from reference 25M clock (XTAL). 20 * However minimal CPU counter prescaler is 2, so the counter 21 * frequency will be divided by 2, the number is 12.5M 22 */ 23 #define COUNTER_FREQUENCY 12500000 24 25 #define MVEBU_REGS_BASE 0xD0000000 26 27 /***************************************************************************** 28 * MVEBU memory map related constants 29 ***************************************************************************** 30 */ 31 /* Aggregate of all devices in the first GB */ 32 #define DEVICE0_BASE MVEBU_REGS_BASE 33 #define DEVICE0_SIZE 0x10000000 34 35 /***************************************************************************** 36 * GIC-500 & interrupt handling related constants 37 ***************************************************************************** 38 */ 39 /* Base MVEBU compatible GIC memory map */ 40 #define MVEBU_GICD_BASE 0x1D00000 41 #define MVEBU_GICR_BASE 0x1D40000 42 #define MVEBU_GICC_BASE 0x1D80000 43 44 /* 45 * CCI-400 base address 46 * This address is absolute, not relative to MVEBU_REGS_BASE. 47 * This is not the default CCI base address (that would be 0xD8000000). 48 * Rather we remap CCI to this address to better utilize the address space. 49 * (The remapping is done in plat/marvell/armada/a3k/common/plat_cci.c) 50 */ 51 #define MVEBU_CCI_BASE 0xFE000000 52 53 /***************************************************************************** 54 * North and south bridge reset registers 55 ***************************************************************************** 56 */ 57 #define MVEBU_NB_RESET_REG (MVEBU_REGS_BASE + 0x12400) 58 #define MVEBU_NB_RESET_I2C1_N (1 << 0) 59 #define MVEBU_NB_RESET_1WIRE_N (1 << 1) 60 #define MVEBU_NB_RESET_SPI_N (1 << 2) 61 #define MVEBU_NB_RESET_UART_N (1 << 3) 62 #define MVEBU_NB_RESET_XTL_N (1 << 4) 63 #define MVEBU_NB_RESET_I2C2_N (1 << 5) 64 #define MVEBU_NB_RESET_UART2_N (1 << 6) 65 #define MVEBU_NB_RESET_AVS_N (1 << 7) 66 #define MVEBU_NB_RESET_DDR_N (1 << 10) 67 #define MVEBU_NB_RESET_SETM_N (1 << 11) 68 #define MVEBU_NB_RESET_DMA_N (1 << 12) 69 #define MVEBU_NB_RESET_TSECM_N (1 << 13) 70 #define MVEBU_NB_RESET_SDIO_N (1 << 14) 71 #define MVEBU_NB_RESET_SATA_N (1 << 15) 72 #define MVEBU_NB_RESET_PWRMGT_N (1 << 16) 73 #define MVEBU_NB_RESET_OTP_N (1 << 17) 74 #define MVEBU_NB_RESET_EIP_N (1 << 18) 75 #define MVEBU_SB_RESET_REG (MVEBU_REGS_BASE + 0x18600) 76 #define MVEBU_SB_RESET_MCIPHY (1 << 1) 77 #define MVEBU_SB_RESET_SDIO_N (1 << 2) 78 #define MVEBU_SB_RESET_PCIE_N (1 << 3) 79 #define MVEBU_SB_RESET_GBE1_N (1 << 4) 80 #define MVEBU_SB_RESET_GBE0_N (1 << 5) 81 #define MVEBU_SB_RESET_USB2PHY (1 << 6) 82 #define MVEBU_SB_RESET_USB2HPHY (1 << 7) 83 #define MVEBU_SB_RESET_MCI_N (1 << 8) 84 #define MVEBU_SB_RESET_PWRMGT_N (1 << 9) 85 #define MVEBU_SB_RESET_EBM_N (1 << 10) 86 #define MVEBU_SB_RESET_OTP_N (1 << 11) 87 88 /***************************************************************************** 89 * North and south bridge register base 90 ***************************************************************************** 91 */ 92 #define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000) 93 #define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000) 94 95 /***************************************************************************** 96 * GPIO registers related constants 97 ***************************************************************************** 98 */ 99 /* North and south bridge GPIO register base address */ 100 #define MVEBU_NB_GPIO_REG_BASE (MVEBU_NB_REGS_BASE + 0x800) 101 #define MVEBU_NB_GPIO_IRQ_REG_BASE (MVEBU_NB_REGS_BASE + 0xC00) 102 #define MVEBU_SB_GPIO_REG_BASE (MVEBU_SB_REGS_BASE + 0x800) 103 #define MVEBU_SB_GPIO_IRQ_REG_BASE (MVEBU_SB_REGS_BASE + 0xC00) 104 #define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00) 105 106 /* North Bridge GPIO selection register */ 107 #define MVEBU_NB_GPIO_SEL_REG (MVEBU_NB_GPIO_REG_BASE + 0x30) 108 #define MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG (MVEBU_NB_GPIO_REG_BASE + 0x04) 109 /* I2C1 GPIO Enable bit offset */ 110 #define MVEBU_GPIO_TW1_GPIO_EN_OFF (10) 111 /* SPI pins mode bit offset */ 112 #define MVEBU_GPIO_NB_SPI_PIN_MODE_OFF (28) 113 114 /***************************************************************************** 115 * DRAM registers related constants 116 ***************************************************************************** 117 */ 118 #define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE) 119 120 /***************************************************************************** 121 * SB wake-up registers related constants 122 ***************************************************************************** 123 */ 124 #define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000) 125 126 /***************************************************************************** 127 * PMSU registers related constants 128 ***************************************************************************** 129 */ 130 #define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000) 131 132 /***************************************************************************** 133 * North Bridge Step-Down Registers 134 ***************************************************************************** 135 */ 136 #define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800) 137 138 /***************************************************************************** 139 * DRAM CS memory map register base 140 ***************************************************************************** 141 */ 142 #define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200) 143 144 /***************************************************************************** 145 * CPU decoder window registers related constants 146 ***************************************************************************** 147 */ 148 #define MVEBU_CPU_DEC_WIN_REG_BASE (MVEBU_REGS_BASE + 0xCF00) 149 150 /***************************************************************************** 151 * AVS registers related constants 152 ***************************************************************************** 153 */ 154 #define MVEBU_AVS_REG_BASE (MVEBU_REGS_BASE + 0x11500) 155 156 157 /***************************************************************************** 158 * AVS registers related constants 159 ***************************************************************************** 160 */ 161 #define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300) 162 163 /***************************************************************************** 164 * Cortex-M3 Secure Processor Mailbox constants 165 ***************************************************************************** 166 */ 167 #define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000) 168 169 #endif /* A3700_PLAT_DEF_H */ 170