Searched refs:PLAT_MARVELL_MAILBOX_BASE (Results 1 – 9 of 9) sorted by relevance
26 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in marvell_program_mailbox()32 assert((PLAT_MARVELL_MAILBOX_BASE >= MARVELL_SHARED_RAM_BASE) && in marvell_program_mailbox()33 ((PLAT_MARVELL_MAILBOX_BASE + sizeof(*mailbox)) <= in marvell_program_mailbox()41 flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE + in marvell_program_mailbox()
25 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in mailbox_clean()33 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in exec_ble_main()
40 mov_imm x0, PLAT_MARVELL_MAILBOX_BASE
42 mov_imm x0, PLAT_MARVELL_MAILBOX_BASE
106 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in bl31_plat_arch_setup()
623 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend()636 flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + in a8k_pwr_domain_suspend()695 uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; in a8k_pwr_domain_suspend_finish()713 flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + in a8k_pwr_domain_suspend_finish()
186 #define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE \ macro
175 #define PLAT_MARVELL_MAILBOX_BASE (MARVELL_SHARED_RAM_BASE + 0x400) macro
785 mmio_write_32(PLAT_MARVELL_MAILBOX_BASE, 0x0); in a3700_system_reset()791 flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, in a3700_system_reset()
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