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Searched refs:PLL_CONS (Results 1 – 7 of 7) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/soc/
A Dsoc.c133 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); in plls_suspend()
147 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in plls_resume()
149 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in plls_resume()
151 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in plls_resume()
153 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in plls_resume()
155 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), in plls_resume()
175 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), in pm_plls_resume()
177 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), in pm_plls_resume()
179 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), in pm_plls_resume()
181 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), in pm_plls_resume()
[all …]
A Dsoc.h119 #define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/
A Dpmu.c286 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
289 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
292 mmio_write_32(CRU_BASE + PLL_CONS(pll_id, 1), in pll_pwr_dwn()
306 mmio_read_32(CRU_BASE + PLL_CONS(DPLL_ID, i)); in dpll_suspend()
307 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
309 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_suspend()
317 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
319 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
321 mmio_write_32(CRU_BASE + PLL_CONS(DPLL_ID, 1), in dpll_resume()
350 mmio_read_32(CRU_BASE + PLL_CONS(pll_id, i)); in pll_suspend()
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/soc/
A Dsoc.c109 pll[0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); in pll_save()
110 pll[1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); in pll_save()
111 pll[2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); in pll_save()
112 pll[3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); in pll_save()
A Dsoc.h65 #define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) macro
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/ddr/
A Dddr_rk3368.c390 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
394 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3); in ddr_reg_save()
397 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0); in ddr_reg_save()
401 PLL_CONS(DPLL_ID, 0)) in ddr_reg_save()
405 PLL_CONS(DPLL_ID, 1)) in ddr_reg_save()
408 PLL_CONS(DPLL_ID, 2)) in ddr_reg_save()
411 PLL_CONS(DPLL_ID, 3)) in ddr_reg_save()
419 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1); in ddr_reg_save()
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/
A Dsoc.h39 #define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4)) macro

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