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Searched refs:PLL_MODE (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/m0/src/
A Ddram.c43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/include/shared/
A Dmisc_regs.h21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl.c19 enum pll_set_rate_mode PLL_MODE = CON0_PCW; variable
251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()

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