Searched refs:PLL_SLOW_MODE (Results 1 – 8 of 8) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/include/shared/ |
| A D | misc_regs.h | 19 #define PLL_SLOW_MODE 0 macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/ |
| A D | pmu.c | 195 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(CPLL_ID)); in rockchip_soc_soft_reset()
196 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(GPLL_ID)); in rockchip_soc_soft_reset()
197 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(NPLL_ID)); in rockchip_soc_soft_reset()
198 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(APLL_ID)); in rockchip_soc_soft_reset()
301 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(DPLL_ID)); in dpll_suspend()
345 mmio_write_32(CRU_BASE + CRU_CRU_MODE, PLL_SLOW_MODE(pll_id)); in pll_suspend()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/soc/ |
| A D | soc.c | 56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
59 CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in set_pll_slow_mode()
126 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in restore_pll()
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| A D | soc.h | 35 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/m0/src/ |
| A D | dram.c | 43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.h | 54 #define PLL_SLOW_MODE(id) ((id) == NPLL_ID) ? \ macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 655 mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE); in pmusram_restore_pll()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/pmu/ |
| A D | pmu.c | 587 PLL_SLOW_MODE); in clst_pwr_domain_suspend()
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