| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/m0/src/ |
| A D | suspend.c | 25 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main()
44 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
46 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
53 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
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| A D | dram.c | 21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port()
23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port()
31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/pmu/ |
| A D | pmu.c | 36 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) in rk3368_flash_l2_b()
41 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); in rk3368_flash_l2_b()
146 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3368_pmu_bus_idle()
152 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3368_pmu_bus_idle()
154 while ((mmio_read_32(PMU_BASE + in rk3368_pmu_bus_idle()
159 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3368_pmu_bus_idle()
176 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn()
186 while (!(mmio_read_32(PMU_BASE + in pmu_scu_b_pwrdn()
191 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); in pmu_scu_b_pwrdn()
221 mmio_write_32(PMU_BASE + PMU_PWRMD_COM, pwrmd_com); in pmu_sleep_mode_config()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/pmu/ |
| A D | pmu.c | 103 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3288_pmu_bus_idle()
109 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3288_pmu_bus_idle()
111 while ((mmio_read_32(PMU_BASE + in rk3288_pmu_bus_idle()
116 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3288_pmu_bus_idle()
170 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
180 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 32 * 30); in pmu_set_sleep_mode()
183 mmio_write_32(PMU_BASE + PMU_OSC_CNT, in pmu_set_sleep_mode()
193 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
198 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 24000 * 30); in pmu_set_sleep_mode()
201 mmio_write_32(PMU_BASE + PMU_OSC_CNT, 0); in pmu_set_sleep_mode()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/drivers/pmu/ |
| A D | pmu.c | 138 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, in pmu_power_domain_ctr()
167 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_REQ, in pmu_bus_idle_req()
758 mmio_write_32(PMU_BASE + PMU_OSC_CNT_LO, in pmu_sleep_config()
760 mmio_write_32(PMU_BASE + PMU_OSC_CNT_HI, in pmu_sleep_config()
763 mmio_write_32(PMU_BASE + PMU_STABLE_CNT_LO, in pmu_sleep_config()
765 mmio_write_32(PMU_BASE + PMU_STABLE_CNT_HI, in pmu_sleep_config()
787 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT_LO, in pmu_sleep_config()
792 mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_LO, in pmu_sleep_config()
794 mmio_write_32(PMU_BASE + PMU_PLLRST_CNT_HI, in pmu_sleep_config()
808 mmio_write_32(PMU_BASE + PMU_WKUP_CFG2_LO, in pmu_sleep_config()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/pmu/ |
| A D | pmu.c | 97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), in pmu_bus_idle_req()
100 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), in pmu_bus_idle_req()
448 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn()
850 mmio_write_32(PMU_BASE + PMU_CCI500_CON, in sys_slp_config()
855 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in sys_slp_config()
1382 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in rockchip_soc_sys_pwr_dm_suspend()
1390 while ((mmio_read_32(PMU_BASE + in rockchip_soc_sys_pwr_dm_suspend()
1463 mmio_write_32(PMU_BASE + PMU_CCI500_CON, in rockchip_soc_sys_pwr_dm_resume()
1468 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON, in rockchip_soc_sys_pwr_dm_resume()
1471 mmio_write_32(PMU_BASE + PMU_ADB400_CON, in rockchip_soc_sys_pwr_dm_resume()
[all …]
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| A D | plat_pmu_macros.S | 89 mov x5, PMU_BASE
116 mov x5, PMU_BASE
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/drivers/pmu/ |
| A D | pmu_com.h | 11 #define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST)
40 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); in pmu_power_domain_st()
56 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); in pmu_power_domain_ctr()
62 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); in pmu_power_domain_ctr()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/pmu/ |
| A D | pmu.c | 41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
509 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in ddr_suspend()
514 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(2)); in ddr_suspend()
544 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(2)); in dmc_restore()
546 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in dmc_restore()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/ |
| A D | rk3368_def.h | 31 #define PMU_BASE 0xff730000 macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/ |
| A D | rk3288_def.h | 54 #define PMU_BASE 0xff730000 macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/ |
| A D | rk3328_def.h | 27 #define PMU_BASE 0xff140000 macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/px30/ |
| A D | px30_def.h | 21 #define PMU_BASE 0xff000000 macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/include/shared/ |
| A D | addressmap_shared.h | 26 #define PMU_BASE (MMIO_BASE + 0x07310000) macro
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3328/drivers/soc/ |
| A D | soc.c | 28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 598 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); in pctl_start()
600 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); in pctl_start()
691 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()
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| A D | dfs.c | 1756 low_power |= ((mmio_read_32(PMU_BASE + PMU_SFT_CON) >> tmp) & in exit_low_power()
1758 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 1 << tmp); in exit_low_power()
1759 while (!(mmio_read_32(PMU_BASE + PMU_DDR_SREF_ST) & (1 << i))) in exit_low_power()
1792 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, val << tmp); in resume_low_power()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3288/drivers/soc/ |
| A D | soc.c | 35 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/soc/ |
| A D | soc.c | 31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3368/drivers/ddr/ |
| A D | ddr_rk3368.c | 428 p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM; in ddr_reg_save()
|