1 /* 2 * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved. 3 * Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef __PNCD_PRIVATE_H__ 9 #define __PNCD_PRIVATE_H__ 10 11 #ifndef __ASSEMBLER__ 12 #include <stdint.h> 13 #endif /* __ASSEMBLER __ */ 14 15 #include <context.h> 16 #ifndef __ASSEMBLER__ 17 #include <lib/cassert.h> 18 #endif /* __ASSEMBLER __ */ 19 20 #include <platform_def.h> 21 22 /******************************************************************************* 23 * Constants that allow assembler code to preserve callee-saved registers of the 24 * C runtime context while performing a security state switch. 25 ******************************************************************************/ 26 #define PNCD_C_RT_CTX_X19 U(0x0) 27 #define PNCD_C_RT_CTX_X20 U(0x8) 28 #define PNCD_C_RT_CTX_X21 U(0x10) 29 #define PNCD_C_RT_CTX_X22 U(0x18) 30 #define PNCD_C_RT_CTX_X23 U(0x20) 31 #define PNCD_C_RT_CTX_X24 U(0x28) 32 #define PNCD_C_RT_CTX_X25 U(0x30) 33 #define PNCD_C_RT_CTX_X26 U(0x38) 34 #define PNCD_C_RT_CTX_X27 U(0x40) 35 #define PNCD_C_RT_CTX_X28 U(0x48) 36 #define PNCD_C_RT_CTX_X29 U(0x50) 37 #define PNCD_C_RT_CTX_X30 U(0x58) 38 #define PNCD_C_RT_CTX_SIZE U(0x60) 39 #define PNCD_C_RT_CTX_ENTRIES (PNCD_C_RT_CTX_SIZE >> DWORD_SHIFT) 40 41 #ifndef __ASSEMBLER__ 42 43 /* AArch64 callee saved general purpose register context structure. */ 44 DEFINE_REG_STRUCT(c_rt_regs, PNCD_C_RT_CTX_ENTRIES); 45 46 /* 47 * Compile time assertion to ensure that both the compiler and linker 48 * have the same double word aligned view of the size of the C runtime 49 * register context. 50 */ 51 CASSERT(sizeof(c_rt_regs_t) == PNCD_C_RT_CTX_SIZE, 52 assert_spd_c_rt_regs_size_mismatch); 53 54 /******************************************************************************* 55 * Structure which helps the SPD to maintain the per-cpu state of the SP. 56 * 'mpidr' - mpidr of the CPU running PNC 57 * 'c_rt_ctx' - stack address to restore C runtime context from after 58 * returning from a synchronous entry into the SP. 59 * 'cpu_ctx' - space to maintain SP architectural state 60 ******************************************************************************/ 61 typedef struct pnc_context { 62 uint64_t mpidr; 63 uint64_t c_rt_ctx; 64 cpu_context_t cpu_ctx; 65 } pnc_context_t; 66 67 /******************************************************************************* 68 * Function & Data prototypes 69 ******************************************************************************/ 70 uint64_t pncd_enter_sp(uint64_t *c_rt_ctx); 71 void __dead2 pncd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 72 uint64_t pncd_synchronous_sp_entry(pnc_context_t *pnc_ctx); 73 void __dead2 pncd_synchronous_sp_exit(pnc_context_t *pnc_ctx, uint64_t ret); 74 void pncd_init_pnc_ep_state(struct entry_point_info *pnc_ep, 75 uint64_t pc, 76 pnc_context_t *pnc_ctx); 77 #endif /* __ASSEMBLER__ */ 78 79 #endif /* __PNCD_PRIVATE_H__ */ 80