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Searched refs:PSCI_CPU_PWR_LVL (Results 1 – 18 of 18) sorted by relevance

/arm-trusted-firmware-2.8.0/lib/psci/
A Dpsci_stat.c87 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_down()
122 local_state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_stats_update_pwr_up()
123 stat_idx = get_stat_idx(local_state, PSCI_CPU_PWR_LVL); in psci_stats_update_pwr_up()
126 residency = plat_psci_stat_get_residency(PSCI_CPU_PWR_LVL, in psci_stats_update_pwr_up()
142 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_stats_update_pwr_up()
210 if (pwrlvl > PSCI_CPU_PWR_LVL) { in psci_get_stat()
213 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl < pwrlvl; lvl++) in psci_get_stat()
A Dpsci_common.c76 (PLAT_MAX_PWR_LVL >= PSCI_CPU_PWR_LVL),
212 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_set_req_local_pwr_state()
213 if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) && in psci_set_req_local_pwr_state()
247 assert(pwrlvl > PSCI_CPU_PWR_LVL); in psci_get_req_local_pwr_states()
312 pd_state[PSCI_CPU_PWR_LVL] = psci_get_cpu_local_state(); in psci_get_target_local_pwr_states()
316 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_get_target_local_pwr_states()
338 psci_set_cpu_local_state(pd_state[PSCI_CPU_PWR_LVL]); in psci_set_target_local_pwr_states()
367 for (i = PSCI_CPU_PWR_LVL + 1U; i <= end_lvl; i++) { in psci_get_parent_pwr_domain_nodes()
385 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_set_pwr_domains_to_run()
434 for (lvl = PSCI_CPU_PWR_LVL + 1U; lvl <= end_pwrlvl; lvl++) { in psci_do_state_coordination()
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A Dpsci_setup.c47 if (level > PSCI_CPU_PWR_LVL) { in psci_init_pwr_domain_node()
140 while (level >= (int) PSCI_CPU_PWR_LVL) { in populate_power_domain_tree()
170 if (level == (int) PSCI_CPU_PWR_LVL) in populate_power_domain_tree()
A Dpsci_off.c26 for (lvl = PSCI_CPU_PWR_LVL; lvl <= PLAT_MAX_PWR_LVL; lvl++) in psci_set_power_off_state()
A Dpsci_main.c95 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL]; in psci_cpu_suspend()
123 psci_stats_update_pwr_up(PSCI_CPU_PWR_LVL, &state_info); in psci_cpu_suspend()
226 if (lowest_affinity_level > PSCI_CPU_PWR_LVL) in psci_affinity_info()
A Dpsci_suspend.c287 state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]) != 0)); in psci_cpu_suspend_finish()
/arm-trusted-firmware-2.8.0/plat/common/
A Dplat_psci_common.c100 assert((lvl >= PSCI_CPU_PWR_LVL) && (lvl <= PLAT_MAX_PWR_LVL)); in plat_psci_stat_get_residency()
104 if (lvl == PSCI_CPU_PWR_LVL) in plat_psci_stat_get_residency()
112 state = state_info->pwr_domain_state[PSCI_CPU_PWR_LVL]; in plat_psci_stat_get_residency()
/arm-trusted-firmware-2.8.0/plat/mediatek/lib/pm/armv8_2/
A Dpwr_ctrl.c94 for (i = (int)PLAT_MAX_PWR_LVL; i >= (int)PSCI_CPU_PWR_LVL; i--) { in armv8_2_get_pwr_afflv()
375 for (i = PSCI_CPU_PWR_LVL; i <= aff_lvl; i++) { in armv8_2_validate_power_state()
398 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = in armv8_2_get_sys_suspend_power_state()
400 for (i = PSCI_CPU_PWR_LVL + 1; i <= PLAT_MAX_PWR_LVL; i++) { in armv8_2_get_sys_suspend_power_state()
404 power_state = psci_make_powerstate(0, PSTATE_TYPE_STANDBY, PSCI_CPU_PWR_LVL); in armv8_2_get_sys_suspend_power_state()
406 for (i = PSCI_CPU_PWR_LVL; i <= PLAT_MAX_PWR_LVL; i++) { in armv8_2_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/nxp/common/psci/include/
A Dplat_psci.h19 #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL
/arm-trusted-firmware-2.8.0/plat/intel/soc/common/
A Dsocfpga_psci.c195 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in socfpga_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/xilinx/versal/
A Dplat_psci.c222 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/
A Dplat_psci.c199 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/xilinx/versal_net/
A Dplat_psci_pm.c224 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in versal_net_get_sys_suspend_power_state()
A Dplat_psci.c133 req_state->pwr_domain_state[PSCI_CPU_PWR_LVL] = PLAT_MAX_OFF_STATE; in zynqmp_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/include/lib/psci/
A Dpsci.h30 #define PSCI_CPU_PWR_LVL U(0) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/
A Dplat_pm.c328 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/
A Dplat_pm.c330 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/
A Dplat_pm.c327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) { in plat_get_sys_suspend_power_state()

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