PU_PGC_DN_TRG (reference) in projects: arm-trusted-firmware-2.8.0

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Searched refs:PU_PGC_DN_TRG (Results 1 – 8 of 8) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/
A D	gpc.c	314 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU2D_PWR_REQ); in imx_gpc_pm_domain_enable() 317 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU2D_PWR_REQ) { in imx_gpc_pm_domain_enable() 324 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, GPU3D_PWR_REQ); in imx_gpc_pm_domain_enable() 327 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & GPU3D_PWR_REQ) { in imx_gpc_pm_domain_enable() 338 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable() 341 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/
A D	dram_retention.c	`17 #define PU_PGC_DN_TRG 0x104 macro 103 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5)); in dram_enter_retention()`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/
A D	gpc.c	`280 mmio_write_32(IMX_GPC_BASE + PU_PGC_DN_TRG, VPU_G1_PWR_REQ \| in imx_gpc_pm_domain_enable() 283 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & (VPU_G1_PWR_REQ \| in imx_gpc_pm_domain_enable() 289 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable() 292 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) in imx_gpc_pm_domain_enable()`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/
A D	gpc.c	`132 mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, pwr_domain->pwr_req); in imx_gpc_pm_domain_enable() 135 while (mmio_read_32(IMX_GPC_BASE + PU_PGC_DN_TRG) & pwr_domain->pwr_req) { in imx_gpc_pm_domain_enable()`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mq/include/
A D	gpc_reg.h	`29 #define PU_PGC_DN_TRG 0x104 macro`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mn/include/
A D	gpc_reg.h	`29 #define PU_PGC_DN_TRG 0x104 macro`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mm/include/
A D	gpc_reg.h	`29 #define PU_PGC_DN_TRG 0x104 macro`
/arm-trusted-firmware-2.8.0/plat/imx/imx8m/imx8mp/include/
A D	gpc_reg.h	`30 #define PU_PGC_DN_TRG 0xE4 macro`

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