1 /*
2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
5 */
6
7 #include <inttypes.h>
8
9 #include <common/debug.h>
10 #include <common/fdt_wrappers.h>
11 #include <drivers/clk.h>
12 #include <drivers/delay_timer.h>
13 #include <drivers/spi_mem.h>
14 #include <drivers/st/stm32_gpio.h>
15 #include <drivers/st/stm32_qspi.h>
16 #include <drivers/st/stm32mp_reset.h>
17 #include <lib/mmio.h>
18 #include <lib/utils_def.h>
19 #include <libfdt.h>
20
21 #include <platform_def.h>
22
23 /* Timeout for device interface reset */
24 #define TIMEOUT_US_1_MS 1000U
25
26 /* QUADSPI registers */
27 #define QSPI_CR 0x00U
28 #define QSPI_DCR 0x04U
29 #define QSPI_SR 0x08U
30 #define QSPI_FCR 0x0CU
31 #define QSPI_DLR 0x10U
32 #define QSPI_CCR 0x14U
33 #define QSPI_AR 0x18U
34 #define QSPI_ABR 0x1CU
35 #define QSPI_DR 0x20U
36 #define QSPI_PSMKR 0x24U
37 #define QSPI_PSMAR 0x28U
38 #define QSPI_PIR 0x2CU
39 #define QSPI_LPTR 0x30U
40
41 /* QUADSPI control register */
42 #define QSPI_CR_EN BIT(0)
43 #define QSPI_CR_ABORT BIT(1)
44 #define QSPI_CR_DMAEN BIT(2)
45 #define QSPI_CR_TCEN BIT(3)
46 #define QSPI_CR_SSHIFT BIT(4)
47 #define QSPI_CR_DFM BIT(6)
48 #define QSPI_CR_FSEL BIT(7)
49 #define QSPI_CR_FTHRES_SHIFT 8U
50 #define QSPI_CR_TEIE BIT(16)
51 #define QSPI_CR_TCIE BIT(17)
52 #define QSPI_CR_FTIE BIT(18)
53 #define QSPI_CR_SMIE BIT(19)
54 #define QSPI_CR_TOIE BIT(20)
55 #define QSPI_CR_APMS BIT(22)
56 #define QSPI_CR_PMM BIT(23)
57 #define QSPI_CR_PRESCALER_MASK GENMASK_32(31, 24)
58 #define QSPI_CR_PRESCALER_SHIFT 24U
59
60 /* QUADSPI device configuration register */
61 #define QSPI_DCR_CKMODE BIT(0)
62 #define QSPI_DCR_CSHT_MASK GENMASK_32(10, 8)
63 #define QSPI_DCR_CSHT_SHIFT 8U
64 #define QSPI_DCR_FSIZE_MASK GENMASK_32(20, 16)
65 #define QSPI_DCR_FSIZE_SHIFT 16U
66
67 /* QUADSPI status register */
68 #define QSPI_SR_TEF BIT(0)
69 #define QSPI_SR_TCF BIT(1)
70 #define QSPI_SR_FTF BIT(2)
71 #define QSPI_SR_SMF BIT(3)
72 #define QSPI_SR_TOF BIT(4)
73 #define QSPI_SR_BUSY BIT(5)
74
75 /* QUADSPI flag clear register */
76 #define QSPI_FCR_CTEF BIT(0)
77 #define QSPI_FCR_CTCF BIT(1)
78 #define QSPI_FCR_CSMF BIT(3)
79 #define QSPI_FCR_CTOF BIT(4)
80
81 /* QUADSPI communication configuration register */
82 #define QSPI_CCR_DDRM BIT(31)
83 #define QSPI_CCR_DHHC BIT(30)
84 #define QSPI_CCR_SIOO BIT(28)
85 #define QSPI_CCR_FMODE_SHIFT 26U
86 #define QSPI_CCR_DMODE_SHIFT 24U
87 #define QSPI_CCR_DCYC_SHIFT 18U
88 #define QSPI_CCR_ABSIZE_SHIFT 16U
89 #define QSPI_CCR_ABMODE_SHIFT 14U
90 #define QSPI_CCR_ADSIZE_SHIFT 12U
91 #define QSPI_CCR_ADMODE_SHIFT 10U
92 #define QSPI_CCR_IMODE_SHIFT 8U
93 #define QSPI_CCR_IND_WRITE 0U
94 #define QSPI_CCR_IND_READ 1U
95 #define QSPI_CCR_MEM_MAP 3U
96
97 #define QSPI_MAX_CHIP 2U
98
99 #define QSPI_FIFO_TIMEOUT_US 30U
100 #define QSPI_CMD_TIMEOUT_US 1000U
101 #define QSPI_BUSY_TIMEOUT_US 100U
102 #define QSPI_ABT_TIMEOUT_US 100U
103
104 #define DT_QSPI_COMPAT "st,stm32f469-qspi"
105
106 #define FREQ_100MHZ 100000000U
107
108 struct stm32_qspi_ctrl {
109 uintptr_t reg_base;
110 uintptr_t mm_base;
111 size_t mm_size;
112 unsigned long clock_id;
113 unsigned int reset_id;
114 };
115
116 static struct stm32_qspi_ctrl stm32_qspi;
117
qspi_base(void)118 static uintptr_t qspi_base(void)
119 {
120 return stm32_qspi.reg_base;
121 }
122
stm32_qspi_wait_for_not_busy(void)123 static int stm32_qspi_wait_for_not_busy(void)
124 {
125 uint64_t timeout = timeout_init_us(QSPI_BUSY_TIMEOUT_US);
126
127 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_BUSY) != 0U) {
128 if (timeout_elapsed(timeout)) {
129 ERROR("%s: busy timeout\n", __func__);
130 return -ETIMEDOUT;
131 }
132 }
133
134 return 0;
135 }
136
stm32_qspi_wait_cmd(const struct spi_mem_op * op)137 static int stm32_qspi_wait_cmd(const struct spi_mem_op *op)
138 {
139 int ret = 0;
140 uint64_t timeout;
141
142 timeout = timeout_init_us(QSPI_CMD_TIMEOUT_US);
143 while ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TCF) == 0U) {
144 if (timeout_elapsed(timeout)) {
145 ret = -ETIMEDOUT;
146 break;
147 }
148 }
149
150 if (ret == 0) {
151 if ((mmio_read_32(qspi_base() + QSPI_SR) & QSPI_SR_TEF) != 0U) {
152 ERROR("%s: transfer error\n", __func__);
153 ret = -EIO;
154 }
155 } else {
156 ERROR("%s: cmd timeout\n", __func__);
157 }
158
159 /* Clear flags */
160 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF | QSPI_FCR_CTEF);
161
162 if (ret == 0) {
163 ret = stm32_qspi_wait_for_not_busy();
164 }
165
166 return ret;
167 }
168
stm32_qspi_read_fifo(uint8_t * val,uintptr_t addr)169 static void stm32_qspi_read_fifo(uint8_t *val, uintptr_t addr)
170 {
171 *val = mmio_read_8(addr);
172 }
173
stm32_qspi_write_fifo(uint8_t * val,uintptr_t addr)174 static void stm32_qspi_write_fifo(uint8_t *val, uintptr_t addr)
175 {
176 mmio_write_8(addr, *val);
177 }
178
stm32_qspi_poll(const struct spi_mem_op * op)179 static int stm32_qspi_poll(const struct spi_mem_op *op)
180 {
181 void (*fifo)(uint8_t *val, uintptr_t addr);
182 uint32_t len;
183 uint8_t *buf;
184
185 if (op->data.dir == SPI_MEM_DATA_IN) {
186 fifo = stm32_qspi_read_fifo;
187 } else {
188 fifo = stm32_qspi_write_fifo;
189 }
190
191 buf = (uint8_t *)op->data.buf;
192
193 for (len = op->data.nbytes; len != 0U; len--) {
194 uint64_t timeout = timeout_init_us(QSPI_FIFO_TIMEOUT_US);
195
196 while ((mmio_read_32(qspi_base() + QSPI_SR) &
197 QSPI_SR_FTF) == 0U) {
198 if (timeout_elapsed(timeout)) {
199 ERROR("%s: fifo timeout\n", __func__);
200 return -ETIMEDOUT;
201 }
202 }
203
204 fifo(buf++, qspi_base() + QSPI_DR);
205 }
206
207 return 0;
208 }
209
stm32_qspi_mm(const struct spi_mem_op * op)210 static int stm32_qspi_mm(const struct spi_mem_op *op)
211 {
212 memcpy(op->data.buf,
213 (void *)(stm32_qspi.mm_base + (size_t)op->addr.val),
214 op->data.nbytes);
215
216 return 0;
217 }
218
stm32_qspi_tx(const struct spi_mem_op * op,uint8_t mode)219 static int stm32_qspi_tx(const struct spi_mem_op *op, uint8_t mode)
220 {
221 if (op->data.nbytes == 0U) {
222 return 0;
223 }
224
225 if (mode == QSPI_CCR_MEM_MAP) {
226 return stm32_qspi_mm(op);
227 }
228
229 return stm32_qspi_poll(op);
230 }
231
stm32_qspi_get_mode(uint8_t buswidth)232 static unsigned int stm32_qspi_get_mode(uint8_t buswidth)
233 {
234 if (buswidth == 4U) {
235 return 3U;
236 }
237
238 return buswidth;
239 }
240
stm32_qspi_exec_op(const struct spi_mem_op * op)241 static int stm32_qspi_exec_op(const struct spi_mem_op *op)
242 {
243 uint64_t timeout;
244 uint32_t ccr;
245 size_t addr_max;
246 uint8_t mode = QSPI_CCR_IND_WRITE;
247 int ret;
248
249 VERBOSE("%s: cmd:%x mode:%d.%d.%d.%d addr:%" PRIx64 " len:%x\n",
250 __func__, op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
251 op->dummy.buswidth, op->data.buswidth,
252 op->addr.val, op->data.nbytes);
253
254 addr_max = op->addr.val + op->data.nbytes + 1U;
255
256 if ((op->data.dir == SPI_MEM_DATA_IN) && (op->data.nbytes != 0U)) {
257 if ((addr_max < stm32_qspi.mm_size) &&
258 (op->addr.buswidth != 0U)) {
259 mode = QSPI_CCR_MEM_MAP;
260 } else {
261 mode = QSPI_CCR_IND_READ;
262 }
263 }
264
265 if (op->data.nbytes != 0U) {
266 mmio_write_32(qspi_base() + QSPI_DLR, op->data.nbytes - 1U);
267 }
268
269 ccr = mode << QSPI_CCR_FMODE_SHIFT;
270 ccr |= op->cmd.opcode;
271 ccr |= stm32_qspi_get_mode(op->cmd.buswidth) << QSPI_CCR_IMODE_SHIFT;
272
273 if (op->addr.nbytes != 0U) {
274 ccr |= (op->addr.nbytes - 1U) << QSPI_CCR_ADSIZE_SHIFT;
275 ccr |= stm32_qspi_get_mode(op->addr.buswidth) <<
276 QSPI_CCR_ADMODE_SHIFT;
277 }
278
279 if ((op->dummy.buswidth != 0U) && (op->dummy.nbytes != 0U)) {
280 ccr |= (op->dummy.nbytes * 8U / op->dummy.buswidth) <<
281 QSPI_CCR_DCYC_SHIFT;
282 }
283
284 if (op->data.nbytes != 0U) {
285 ccr |= stm32_qspi_get_mode(op->data.buswidth) <<
286 QSPI_CCR_DMODE_SHIFT;
287 }
288
289 mmio_write_32(qspi_base() + QSPI_CCR, ccr);
290
291 if ((op->addr.nbytes != 0U) && (mode != QSPI_CCR_MEM_MAP)) {
292 mmio_write_32(qspi_base() + QSPI_AR, op->addr.val);
293 }
294
295 ret = stm32_qspi_tx(op, mode);
296
297 /*
298 * Abort in:
299 * - Error case.
300 * - Memory mapped read: prefetching must be stopped if we read the last
301 * byte of device (device size - fifo size). If device size is not
302 * known then prefetching is always stopped.
303 */
304 if ((ret != 0) || (mode == QSPI_CCR_MEM_MAP)) {
305 goto abort;
306 }
307
308 /* Wait end of TX in indirect mode */
309 ret = stm32_qspi_wait_cmd(op);
310 if (ret != 0) {
311 goto abort;
312 }
313
314 return 0;
315
316 abort:
317 mmio_setbits_32(qspi_base() + QSPI_CR, QSPI_CR_ABORT);
318
319 /* Wait clear of abort bit by hardware */
320 timeout = timeout_init_us(QSPI_ABT_TIMEOUT_US);
321 while ((mmio_read_32(qspi_base() + QSPI_CR) & QSPI_CR_ABORT) != 0U) {
322 if (timeout_elapsed(timeout)) {
323 ret = -ETIMEDOUT;
324 break;
325 }
326 }
327
328 mmio_write_32(qspi_base() + QSPI_FCR, QSPI_FCR_CTCF);
329
330 if (ret != 0) {
331 ERROR("%s: exec op error\n", __func__);
332 }
333
334 return ret;
335 }
336
stm32_qspi_claim_bus(unsigned int cs)337 static int stm32_qspi_claim_bus(unsigned int cs)
338 {
339 uint32_t cr;
340
341 if (cs >= QSPI_MAX_CHIP) {
342 return -ENODEV;
343 }
344
345 /* Set chip select and enable the controller */
346 cr = QSPI_CR_EN;
347 if (cs == 1U) {
348 cr |= QSPI_CR_FSEL;
349 }
350
351 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_FSEL, cr);
352
353 return 0;
354 }
355
stm32_qspi_release_bus(void)356 static void stm32_qspi_release_bus(void)
357 {
358 mmio_clrbits_32(qspi_base() + QSPI_CR, QSPI_CR_EN);
359 }
360
stm32_qspi_set_speed(unsigned int hz)361 static int stm32_qspi_set_speed(unsigned int hz)
362 {
363 unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id);
364 uint32_t prescaler = UINT8_MAX;
365 uint32_t csht;
366 int ret;
367
368 if (qspi_clk == 0U) {
369 return -EINVAL;
370 }
371
372 if (hz > 0U) {
373 prescaler = div_round_up(qspi_clk, hz) - 1U;
374 if (prescaler > UINT8_MAX) {
375 prescaler = UINT8_MAX;
376 }
377 }
378
379 csht = div_round_up((5U * qspi_clk) / (prescaler + 1U), FREQ_100MHZ);
380 csht = ((csht - 1U) << QSPI_DCR_CSHT_SHIFT) & QSPI_DCR_CSHT_MASK;
381
382 ret = stm32_qspi_wait_for_not_busy();
383 if (ret != 0) {
384 return ret;
385 }
386
387 mmio_clrsetbits_32(qspi_base() + QSPI_CR, QSPI_CR_PRESCALER_MASK,
388 prescaler << QSPI_CR_PRESCALER_SHIFT);
389
390 mmio_clrsetbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CSHT_MASK, csht);
391
392 VERBOSE("%s: speed=%lu\n", __func__, qspi_clk / (prescaler + 1U));
393
394 return 0;
395 }
396
stm32_qspi_set_mode(unsigned int mode)397 static int stm32_qspi_set_mode(unsigned int mode)
398 {
399 int ret;
400
401 ret = stm32_qspi_wait_for_not_busy();
402 if (ret != 0) {
403 return ret;
404 }
405
406 if ((mode & SPI_CS_HIGH) != 0U) {
407 return -ENODEV;
408 }
409
410 if (((mode & SPI_CPHA) != 0U) && ((mode & SPI_CPOL) != 0U)) {
411 mmio_setbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);
412 } else if (((mode & SPI_CPHA) == 0U) && ((mode & SPI_CPOL) == 0U)) {
413 mmio_clrbits_32(qspi_base() + QSPI_DCR, QSPI_DCR_CKMODE);
414 } else {
415 return -ENODEV;
416 }
417
418 VERBOSE("%s: mode=0x%x\n", __func__, mode);
419
420 if ((mode & SPI_RX_QUAD) != 0U) {
421 VERBOSE("rx: quad\n");
422 } else if ((mode & SPI_RX_DUAL) != 0U) {
423 VERBOSE("rx: dual\n");
424 } else {
425 VERBOSE("rx: single\n");
426 }
427
428 if ((mode & SPI_TX_QUAD) != 0U) {
429 VERBOSE("tx: quad\n");
430 } else if ((mode & SPI_TX_DUAL) != 0U) {
431 VERBOSE("tx: dual\n");
432 } else {
433 VERBOSE("tx: single\n");
434 }
435
436 return 0;
437 }
438
439 static const struct spi_bus_ops stm32_qspi_bus_ops = {
440 .claim_bus = stm32_qspi_claim_bus,
441 .release_bus = stm32_qspi_release_bus,
442 .set_speed = stm32_qspi_set_speed,
443 .set_mode = stm32_qspi_set_mode,
444 .exec_op = stm32_qspi_exec_op,
445 };
446
stm32_qspi_init(void)447 int stm32_qspi_init(void)
448 {
449 size_t size;
450 int qspi_node;
451 struct dt_node_info info;
452 void *fdt = NULL;
453 int ret;
454
455 if (fdt_get_address(&fdt) == 0) {
456 return -FDT_ERR_NOTFOUND;
457 }
458
459 qspi_node = dt_get_node(&info, -1, DT_QSPI_COMPAT);
460 if (qspi_node < 0) {
461 ERROR("No QSPI ctrl found\n");
462 return -FDT_ERR_NOTFOUND;
463 }
464
465 if (info.status == DT_DISABLED) {
466 return -FDT_ERR_NOTFOUND;
467 }
468
469 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi",
470 &stm32_qspi.reg_base, &size);
471 if (ret != 0) {
472 return ret;
473 }
474
475 ret = fdt_get_reg_props_by_name(fdt, qspi_node, "qspi_mm",
476 &stm32_qspi.mm_base,
477 &stm32_qspi.mm_size);
478 if (ret != 0) {
479 return ret;
480 }
481
482 if (dt_set_pinctrl_config(qspi_node) != 0) {
483 return -FDT_ERR_BADVALUE;
484 }
485
486 if ((info.clock < 0) || (info.reset < 0)) {
487 return -FDT_ERR_BADVALUE;
488 }
489
490 stm32_qspi.clock_id = (unsigned long)info.clock;
491 stm32_qspi.reset_id = (unsigned int)info.reset;
492
493 clk_enable(stm32_qspi.clock_id);
494
495 ret = stm32mp_reset_assert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
496 if (ret != 0) {
497 panic();
498 }
499 ret = stm32mp_reset_deassert(stm32_qspi.reset_id, TIMEOUT_US_1_MS);
500 if (ret != 0) {
501 panic();
502 }
503
504 mmio_write_32(qspi_base() + QSPI_CR, QSPI_CR_SSHIFT);
505 mmio_write_32(qspi_base() + QSPI_DCR, QSPI_DCR_FSIZE_MASK);
506
507 return spi_mem_init_slave(fdt, qspi_node, &stm32_qspi_bus_ops);
508 };
509