Searched refs:REG (Results 1 – 6 of 6) sorted by relevance
| /arm-trusted-firmware-2.8.0/drivers/arm/gic/v3/ |
| A D | gicv3_private.h | 28 #define BIT_NUM(REG, id) \ argument
44 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
46 REG##R_SHIFT) << 2))
50 GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3) : \
52 REG##R_SHIFT) << 3))
59 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
62 (GICD_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 3))
91 BIT_NUM(REG, (id))) & 1U)
121 GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2) : \
129 (GICR_##REG##R + (((uintptr_t)(id) >> REG##R_SHIFT) << 2))
[all …]
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| A D | gicv3_main.c | 51 int_id += (1U << REG##R_SHIFT)) { \
54 REG##R_SHIFT]); \
61 int_id += (1U << REG##R_SHIFT)) { \
63 REG##R_SHIFT] = gicd_read_##reg((base), int_id); \
71 int_id += (1U << REG##R_SHIFT)) { \
74 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
75 >> REG##R_SHIFT]); \
82 int_id += (1U << REG##R_SHIFT)) { \
84 round_up(TOTAL_SPI_INTR_NUM, 1U << REG##R_SHIFT)))\
85 >> REG##R_SHIFT] = gicd_read_##reg((base), int_id);\
[all …]
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/ |
| A D | apupwr_clkctl_def.h | 71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
72 #define apupwr_writel_relax(VAL, REG) mmio_write_32_relax((uintptr_t)REG, VAL) argument
73 #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) argument
74 #define apupwr_clrbits(VAL, REG) mmio_clrbits_32((uintptr_t)REG, VAL) argument
75 #define apupwr_setbits(VAL, REG) mmio_setbits_32((uintptr_t)REG, VAL) argument
76 #define apupwr_clrsetbits(CLR_VAL, SET_VAL, REG) \ argument
77 mmio_clrsetbits_32((uintptr_t)REG, CLR_VAL, SET_VAL)
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/apusys/ |
| A D | mtk_apusys_apc_def.h | 85 #define apuapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
86 #define apuapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/devapc/ |
| A D | devapc.h | 173 #define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) argument
174 #define devapc_readl(REG) mmio_read_32((uintptr_t)REG) argument
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 44 {0x00000000ffe00000, 0x000000000100000, PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
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