| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | romlib-design.rst | 1 Library at ROM
4 This document provides an overview of the "library at ROM" implementation in
12 ROM. The "library at ROM" contains a jump table with the list of functions that
13 are placed in ROM. The capabilities of the "library at ROM" are:
17 2. Functions can be patched after they have been programmed into ROM.
19 3. Platform-specific libraries can be placed in ROM.
37 function -- Name of the function to be placed in library at ROM
102 Patching of functions in library at ROM
108 "library at ROM" version of this function.
132 Build library at ROM
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| /arm-trusted-firmware-2.8.0/bl1/ |
| A D | bl1.ld.S | 23 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
41 } >ROM
46 } >ROM
50 } >ROM
69 } >ROM
88 } >ROM
98 DATA_SECTION >RAM AT>ROM
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| /arm-trusted-firmware-2.8.0/bl2/ |
| A D | bl2_el3.ld.S | 16 ROM (rx): ORIGIN = BL2_RO_BASE, LENGTH = BL2_RO_LIMIT - BL2_RO_BASE
29 #define ROM RAM macro
55 } >ROM
65 } >ROM
91 } >ROM
109 DATA_SECTION >RAM AT>ROM
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| /arm-trusted-firmware-2.8.0/lib/romlib/ |
| A D | romlib.ld.S | 11 ROM (rx): ORIGIN = ROMLIB_RO_BASE, LENGTH = ROMLIB_RO_LIMIT - ROMLIB_RO_BASE
26 } >ROM
34 } >RAM AT>ROM
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | intel-agilex.rst | 6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
11 Boot ROM --> Trusted Firmware-A --> UEFI
45 BL33=PEI.ROM
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| A D | intel-stratix10.rst | 6 Upon boot, Boot ROM loads bl2 into OCRAM. Bl2 subsequently initializes
11 Boot ROM --> Trusted Firmware-A --> UEFI
45 BL33=PEI.ROM
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| A D | socionext-uniphier.rst | 7 UniPhier SoC family implements its internal boot ROM, which loads 64KB [1]_
10 It is useful for platforms with non-TF-A boot ROM, like UniPhier. Here, a
27 ROM (and verified if the chip fuses are blown).
33 1. The Boot ROM
35 This is hard-wired ROM, so never corrupted. It loads the UniPhier BL (with
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| A D | stm32mp1.rst | 49 The STM32MP1 resets in the ROM code of the Cortex-A7.
52 The ROM code boot sequence loads the TF-A binary image from boot device
56 for ROM code is able to load this image.
62 Only BL2 (with STM32 header) is loaded by ROM code. The other binaries are
73 | | ROM
110 ROM code -> BL2 (compiled with BL2_AT_EL3) -> BL32 (SP_min) -> BL33 (U-Boot)
114 ROM code -> BL2 (compiled with BL2_AT_EL3) -> OP-TEE -> BL33 (U-Boot)
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| A D | brcm-stingray.rst | 10 On Poweron, Boot ROM will load bl2 image and Bl2 will initialize the hardware,
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| A D | imx8.rst | 54 with certain offset for BOOT ROM. The system controller firmware,
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| A D | imx8m.rst | 47 with certain offset for BOOT ROM. the u-boot and imx-mkimage will be upstreamed
76 Boot (HABv4), which is implemented via ROM Vector Table (RVT) API to
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| A D | synquacer.rst | 90 - The firmware image, which comprises the option ROM, ARM trusted firmware and
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| A D | rpi4.rst | 60 run after the SoC gets its power. The on-chip Boot ROM loads the next stage
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| A D | qti-msm8916.rst | 46 Boot ROM (PBL) -> SBL -> BL31 (EL3) -> U-Boot (EL2) -> Linux (EL2)
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ |
| A D | soc.def | 43 # Area of OCRAM reserved by ROM code
62 # After BL2 bin, OCRAM is used by ROM Code:
65 # After ROM Code, OCRAM is used by CSF header.
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1046a/ |
| A D | soc.def | 43 # Area of OCRAM reserved by ROM code
62 # After BL2 bin, OCRAM is used by ROM Code:
65 # After ROM Code, OCRAM is used by CSF header.
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1088a/ |
| A D | soc.def | 46 # 0x18000000 - 0x18009fff -> Used by ROM code, (TBD - can it be used for xlat tables)
54 # Area of OCRAM reserved by ROM code
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1028a/ |
| A D | soc.def | 47 # 0x18000000 - 0x18009fff -> Used by ROM code
57 # Area of OCRAM reserved by ROM code
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-lx2160a/ |
| A D | soc.def | 38 # Area of OCRAM reserved by ROM code
79 # 0x18000000 - 0x18009fff -> Used by ROM code
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| /arm-trusted-firmware-2.8.0/docs/resources/diagrams/plantuml/ |
| A D | tfa_dfd.puml | 51 bl1 [label="Boot ROM\n(BL1)" fillcolor="#ddffb3"];
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | image-terminology.rst | 52 AP Boot ROM: ``AP_BL1``
112 SCP Boot ROM: ``SCP_BL1`` (previously ``BL0``)
144 AP Firmware Update Boot ROM: ``AP_NS_BL1U``
188 MCP Boot ROM: ``MCP_BL1``
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 58 Defaults to 0x1000, which is normally in the "ROM" space of the typical
84 as some simple ROM trampoline code (required by the Arm FPGA boot flow) and
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| /arm-trusted-firmware-2.8.0/docs/about/ |
| A D | features.rst | 81 secure system processor, or where a non-TF-A ROM expects BL2 to be loaded
88 in ROM but is accessed through a jump-table that may be stored
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | firmware-design.rst | 53 - Boot Loader stage 1 (BL1) *AP Trusted ROM*
61 - Boot Loader stage 1 (BL1) *AP Trusted ROM*
71 non-trusted SRAM, ROM and DRAM.
504 #. The Boot ROM always jumps to the same address, for both cold
516 cold boot, bypassing the boot ROM for warm boot.
1627 BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1630 relocated from ROM to RAM before executing any C code.
1635 and ``.data`` section in ROM.
1793 Trusted ROM
1833 Trusted ROM
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | drtm_poc.rst | 8 currently used by TF-A covers all firmwares, from the boot ROM to the normal
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