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Searched refs:SCSRSTECR5 (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/renesas/common/include/registers/
A Dcpg_registers.h74 #define SCSRSTECR5 (CPG_BASE + 0x0B94U) macro
/arm-trusted-firmware-2.8.0/plat/renesas/common/
A Dbl2_cpg_init.c100 cpg_write(SCSRSTECR5, reset_cr5); in bl2_secure_cpg_init()

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