Home
last modified time | relevance | path

Searched refs:SID_REG_BASE (Results 1 – 6 of 6) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/arm/board/rdv1/
A Drdv1_plat.c12 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) in plat_arm_sgi_get_platform_id()
18 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); in plat_arm_sgi_get_config_id()
23 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & in plat_arm_sgi_get_multi_chip_mode()
/arm-trusted-firmware-2.8.0/plat/arm/board/rde1edge/
A Drde1edge_plat.c12 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) in plat_arm_sgi_get_platform_id()
18 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); in plat_arm_sgi_get_config_id()
/arm-trusted-firmware-2.8.0/plat/arm/board/rdn1edge/
A Drdn1edge_plat.c45 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) in plat_arm_sgi_get_platform_id()
51 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); in plat_arm_sgi_get_config_id()
56 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & in plat_arm_sgi_get_multi_chip_mode()
/arm-trusted-firmware-2.8.0/plat/arm/board/rdv1mc/
A Drdv1mc_plat.c76 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) in plat_arm_sgi_get_platform_id()
82 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); in plat_arm_sgi_get_config_id()
87 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & in plat_arm_sgi_get_multi_chip_mode()
/arm-trusted-firmware-2.8.0/plat/arm/board/rdn2/
A Drdn2_plat.c87 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET) in plat_arm_sgi_get_platform_id()
93 return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET); in plat_arm_sgi_get_config_id()
98 return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) & in plat_arm_sgi_get_multi_chip_mode()
/arm-trusted-firmware-2.8.0/include/plat/arm/css/common/
A Dcss_def.h29 #define SID_REG_BASE 0x2a4a0000 macro

Completed in 9 milliseconds