1 /* 2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SOCFPGA_SYSTEMMANAGER_H 8 #define SOCFPGA_SYSTEMMANAGER_H 9 10 #include "socfpga_plat_def.h" 11 12 /* System Manager Register Map */ 13 14 #define SOCFPGA_SYSMGR_SDMMC 0x28 15 16 #define SOCFPGA_SYSMGR_FPGAINTF_EN_2 0x6c 17 18 #define SOCFPGA_SYSMGR_EMAC_0 0x44 19 #define SOCFPGA_SYSMGR_EMAC_1 0x48 20 #define SOCFPGA_SYSMGR_EMAC_2 0x4c 21 #define SOCFPGA_SYSMGR_FPGAINTF_EN_3 0x70 22 23 #define SOCFPGA_SYSMGR_NOC_TIMEOUT 0xc0 24 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET 0xc4 25 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR 0xc8 26 #define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL 0xcc 27 #define SOCFPGA_SYSMGR_NOC_IDLEACK 0xd0 28 #define SOCFPGA_SYSMGR_NOC_IDLESTATUS 0xd4 29 30 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0 0x200 31 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1 0x204 32 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2 0x208 33 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_8 0x220 34 #define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_9 0x224 35 36 /* Field Masking */ 37 38 #define SYSMGR_SDMMC_DRVSEL(x) (((x) & 0x7) << 0) 39 #define SYSMGR_SDMMC_SMPLSEL(x) (((x) & 0x7) << 4) 40 41 #define IDLE_DATA_LWSOC2FPGA BIT(4) 42 #define IDLE_DATA_SOC2FPGA BIT(0) 43 #define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA) 44 45 #define SYSMGR_ECC_OCRAM_MASK BIT(1) 46 #define SYSMGR_ECC_DDR0_MASK BIT(16) 47 #define SYSMGR_ECC_DDR1_MASK BIT(17) 48 49 /* Macros */ 50 51 #define SOCFPGA_SYSMGR(_reg) (SOCFPGA_SYSMGR_REG_BASE \ 52 + (SOCFPGA_SYSMGR_##_reg)) 53 54 #endif /* SOCFPGA_SYSTEMMANAGER_H */ 55