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Searched refs:SPM_BASE (Results 1 – 20 of 20) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8188/include/
A Dspm_reg.h13 #define MD32PCM_CFG_BASE (SPM_BASE + 0xA00)
14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
[all …]
A Dplatform_def.h33 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spm/
A Dmt_spm_reg.h23 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
24 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
25 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
26 #define SPM_CLK_CON (SPM_BASE + 0x00C)
27 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
28 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
29 #define PCM_CON0 (SPM_BASE + 0x018)
30 #define PCM_CON1 (SPM_BASE + 0x01C)
31 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
32 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
A Dmt_spm_cond.c20 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spm/
A Dmt_spm_reg.h20 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
21 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
22 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
23 #define SPM_CLK_CON (SPM_BASE + 0x00C)
24 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
25 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
26 #define PCM_CON0 (SPM_BASE + 0x018)
27 #define PCM_CON1 (SPM_BASE + 0x01C)
28 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
29 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
A Dmt_spm_cond.c21 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spm/
A Dmt_spm_reg.h15 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
18 #define SPM_CLK_CON (SPM_BASE + 0x00C)
19 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
21 #define PCM_CON0 (SPM_BASE + 0x018)
22 #define PCM_CON1 (SPM_BASE + 0x01C)
26 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
28 #define PCM_WDT_VAL (SPM_BASE + 0x034)
33 #define MD32_CLK_CON (SPM_BASE + 0x084)
35 #define SPM_SWINT (SPM_BASE + 0x08C)
42 #define SPM_SCP_IRQ (SPM_BASE + 0x0AC)
[all …]
A Dmt_spm_cond.c20 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/drivers/spm/
A Dspm.h9 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
10 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
11 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
12 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
13 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
19 #define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8)
20 #define SPM_PCM_CON0 (SPM_BASE + 0x310)
21 #define SPM_PCM_CON1 (SPM_BASE + 0x314)
22 #define SPM_PCM_IM_PTR (SPM_BASE + 0x318)
23 #define SPM_PCM_IM_LEN (SPM_BASE + 0x31c)
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spm/
A Dspm.h14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define PCM_IM_PTR (SPM_BASE + 0x020)
23 #define PCM_IM_LEN (SPM_BASE + 0x024)
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc_private.h23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
29 #define SPM_PWR_STATUS (SPM_BASE + 0x180)
30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
47 #define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
48 #define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
[all …]
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/include/
A Dplatform_def.h27 #define SPM_BASE (IO_PHYS + 0x00006000) macro
44 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/
A Dplat_dcm.c19 #define PWR_STATUS (SPM_BASE + 0x180)
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/include/
A Dplatform_def.h42 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/include/
A Dplatform_def.h36 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/include/
A Dmt8173_def.h22 #define SPM_BASE (IO_PHYS + 0x6000) macro
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc_private.h32 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc_private.h32 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/
A Dmtspmc_private.h30 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/include/
A Dplatform_def.h19 #define SPM_BASE (IO_PHYS + 0x6000) macro

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