| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spmc/ |
| A D | mtspmc.c | 170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
172 mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
173 mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
176 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
177 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
189 mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
190 mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
191 mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
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| A D | mtspmc_private.h | 106 static const struct per_cpu_reg SPM_CPU_PWR[] = { variable
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/ |
| A D | mtspmc.c | 93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
119 uintptr_t cpu_pwr_con = per_cpu(cluster, cpu, SPM_CPU_PWR); in spm_poweron_cpu()
143 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
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| A D | mtspmc_private.h | 89 static const struct per_cpu_reg SPM_CPU_PWR[] = { variable
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/ |
| A D | mtspmc.c | 98 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
100 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
102 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
104 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
108 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
130 mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweron_cpu()
149 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
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| A D | mtspmc_private.h | 87 static const struct per_cpu_reg SPM_CPU_PWR[] = { variable
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/ |
| A D | mtspmc.c | 93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
111 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
132 mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweron_cpu()
154 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWR_ON); in spm_poweroff_cpu()
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| A D | mtspmc_private.h | 89 static const struct per_cpu_reg SPM_CPU_PWR[] = { variable
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