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Searched refs:SPM_MP0_CPU0_PWR_CON (Results 1 – 5 of 5) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/
A Dmtspmc_private.h70 #define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208) macro
90 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/
A Dmtspmc_private.h70 #define SPM_MP0_CPU0_PWR_CON MCUCFG_REG(0xd208) macro
90 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/
A Dmtspmc_private.h68 #define SPM_MP0_CPU0_PWR_CON SPM_REG(0x208) macro
88 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spmc/
A Dmtspmc_private.h36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208) macro
107 [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/mcusys/v1/
A Dmcucfg.h71 #define SPM_MP0_CPU0_PWR_CON (MCUCFG_BASE + 0xD208) macro

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