Searched refs:STM32MP_DDR_BASE (Results 1 – 8 of 8) sorted by relevance
25 mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN); in stm32mp_ddr_test_rw_access()27 if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { in stm32mp_ddr_test_rw_access()28 return (uint32_t)STM32MP_DDR_BASE; in stm32mp_ddr_test_rw_access()31 mmio_write_32(STM32MP_DDR_BASE, saved_value); in stm32mp_ddr_test_rw_access()49 mmio_write_32(STM32MP_DDR_BASE, pattern); in stm32mp_ddr_test_data_bus()51 if (mmio_read_32(STM32MP_DDR_BASE) != pattern) { in stm32mp_ddr_test_data_bus()52 return (uint32_t)STM32MP_DDR_BASE; in stm32mp_ddr_test_data_bus()89 return (uint32_t)(STM32MP_DDR_BASE + offset); in stm32mp_ddr_test_addr_bus()102 return STM32MP_DDR_BASE; in stm32mp_ddr_test_addr_bus()107 if ((mmio_read_32(STM32MP_DDR_BASE + in stm32mp_ddr_test_addr_bus()[all …]
147 priv->info.base = STM32MP_DDR_BASE; in stm32mp1_ddr_probe()
15 #define DDR_NS_BASE STM32MP_DDR_BASE17 #define DDR_SEC_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SEC_SIZE))
15 #define DDR_NS_BASE STM32MP_DDR_BASE19 #define DDR_SHARE_BASE (STM32MP_DDR_BASE + (DDR_SIZE - DDR_SHARE_SIZE))
90 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, in stm32mp_map_ddr_non_cacheable()97 return mmap_remove_dynamic_region(STM32MP_DDR_BASE, in stm32mp_unmap_ddr()
161 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, in bl2_platform_setup()450 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + in bl2_plat_handle_post_image_load()
123 #define STM32MP_DDR_BASE U(0xC0000000) macro182 #define STM32MP_BL33_BASE STM32MP_DDR_BASE185 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
187 if (entrypoint < STM32MP_DDR_BASE) { in stm32_validate_ns_entrypoint()
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