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Searched refs:SUNXI_R_PRCM_BASE (Results 1 – 10 of 10) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/allwinner/common/
A Dsunxi_common.c139 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, BIT(0)); in sunxi_init_platform_r_twi()
152 mmio_setbits_32(SUNXI_R_PRCM_BASE + 0x28, device_bit); in sunxi_init_platform_r_twi()
154 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, BIT(0)); in sunxi_init_platform_r_twi()
157 mmio_clrbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); in sunxi_init_platform_r_twi()
158 mmio_setbits_32(SUNXI_R_PRCM_BASE + reset_offset, device_bit); in sunxi_init_platform_r_twi()
/arm-trusted-firmware-2.8.0/plat/allwinner/sun50i_a64/include/
A Dsunxi_cpucfg.h25 #define SUNXI_CPU_POWER_CLAMP_REG(c, n) (SUNXI_R_PRCM_BASE + 0x0140 + \
27 #define SUNXI_POWEROFF_GATING_REG(c) (SUNXI_R_PRCM_BASE + 0x0100 + (c) * 4)
A Dsunxi_ccu.h12 #define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0)
A Dsunxi_mmap.h64 #define SUNXI_R_PRCM_BASE 0x01f01400 macro
/arm-trusted-firmware-2.8.0/plat/allwinner/sun50i_h6/include/
A Dsunxi_ccu.h12 #define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
A Dsunxi_mmap.h55 #define SUNXI_R_PRCM_BASE 0x07010000 macro
/arm-trusted-firmware-2.8.0/plat/allwinner/sun50i_h616/include/
A Dsunxi_ccu.h12 #define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
A Dsunxi_mmap.h37 #define SUNXI_R_PRCM_BASE 0x07010000 macro
/arm-trusted-firmware-2.8.0/plat/allwinner/sun50i_r329/include/
A Dsunxi_ccu.h12 #define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290)
A Dsunxi_mmap.h48 #define SUNXI_R_PRCM_BASE 0x07010000 macro

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