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Searched refs:SYSCFG_BASE (Results 1 – 2 of 2) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_syscfg.c134 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL); in enable_io_comp_cell_finish()
142 ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) & in disable_io_comp_cell()
152 value |= mmio_read_32(SYSCFG_BASE + cmpcr_off); in disable_io_comp_cell()
154 mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL); in disable_io_comp_cell()
253 mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR, in enable_high_speed_mode_low_voltage()
320 mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9); in stm32mp1_syscfg_init()
323 bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) & in stm32mp1_syscfg_init()
343 mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR, in stm32mp1_syscfg_enable_io_compensation_start()
388 return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & in stm32mp1_syscfg_get_chip_version()
404 mmio_setbits_32(SYSCFG_BASE + SYSCFG_BOOTCR, SYSCFG_BOOTCR_BMEN); in stm32mp1_syscfg_boot_mode_enable()
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A Dstm32mp1_def.h626 #define SYSCFG_BASE U(0x50020000) macro

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