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Searched refs:TEGRA_PKA1_BASE (Results 1 – 7 of 7) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/drivers/se/
A Dse.c468 se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT); in tegra_se_suspend()
506 mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]); in tegra_se_resume()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/
A Dplat_psci_handlers.c134 se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE + in tegra_soc_pwr_domain_suspend()
415 mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT, in tegra_soc_pwr_domain_on_finish()
A Dplat_setup.c93 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t210/
A Dtegra_def.h271 #define TEGRA_PKA1_BASE U(0x70420000) macro
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t186/
A Dtegra_def.h223 #define TEGRA_PKA1_BASE U(0x03AD0000) macro
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t194/
A Dtegra_def.h184 #define TEGRA_PKA1_BASE U(0x03AD0000) macro
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t194/
A Dplat_setup.c113 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */

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