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Searched refs:UFS_SYS_PHY_CLK_CTRL_REG (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_bl1_setup.c114 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
116 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
124 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
142 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
145 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); in hikey960_ufs_reset()
146 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
A Dhikey960_bl2_setup.c92 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
94 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
102 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
120 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
123 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); in hikey960_ufs_reset()
124 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); in hikey960_ufs_reset()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/include/
A Dhi3660.h321 #define UFS_SYS_PHY_CLK_CTRL_REG (UFS_SYS_REG_BASE + 0x010) macro

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