Searched refs:ULL (Results 1 – 25 of 150) sorted by relevance
123456
16 #define RPI_IO_BASE ULL(0x3F000000)17 #define RPI_IO_SIZE ULL(0x01000000)22 #define RPI3_MBOX_OFFSET ULL(0x0000B880)25 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)26 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)27 #define RPI3_MBOX0_SENDER_OFFSET ULL(0x00000014)43 #define RPI3_IO_PM_OFFSET ULL(0x00100000)46 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)47 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020)48 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024)[all …]
20 #define PLATFORM_STACK_SIZE ULL(0x1000)67 #define SEC_ROM_BASE ULL(0x00000000)68 #define SEC_ROM_SIZE ULL(0x00010000)75 #define SEC_SRAM_BASE ULL(0x00200000)76 #define SEC_SRAM_SIZE ULL(0x00100000)82 #define NS_DRAM0_BASE ULL(0x00400000)83 #define NS_DRAM0_SIZE ULL(0x00C00000)85 #define SEC_ROM_BASE ULL(0x00000000)86 #define SEC_ROM_SIZE ULL(0x00020000)93 #define SEC_SRAM_BASE ULL(0x10000000)[all …]
16 #define RPI_IO_BASE ULL(0xFC000000)17 #define RPI_IO_SIZE ULL(0x04000000)24 #define RPI3_MBOX_OFFSET ULL(0x0000B880)27 #define RPI3_MBOX0_READ_OFFSET ULL(0x00000000)28 #define RPI3_MBOX0_PEEK_OFFSET ULL(0x00000010)45 #define RPI3_IO_PM_OFFSET ULL(0x00100000)48 #define RPI3_PM_RSTC_OFFSET ULL(0x0000001C)49 #define RPI3_PM_RSTS_OFFSET ULL(0x00000020)50 #define RPI3_PM_WDOG_OFFSET ULL(0x00000024)66 #define RPI3_IO_RNG_OFFSET ULL(0x00104000)[all …]
20 #define PLATFORM_STACK_SIZE ULL(0x1000)82 #define PLAT_RPI3_TM_ENTRYPOINT_SIZE ULL(8)87 #define PLAT_RPI3_TM_HOLD_ENTRY_SIZE ULL(8)94 #define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)95 #define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)96 #define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)104 #define PLAT_MAX_BL31_SIZE ULL(0x80000)106 #define BL31_BASE ULL(0x1000)107 #define BL31_LIMIT ULL(0x80000)108 #define BL31_PROGBITS_LIMIT ULL(0x80000)[all …]
42 #define MPIDR_AFFLVL0 ULL(0x0)43 #define MPIDR_AFFLVL1 ULL(0x1)44 #define MPIDR_AFFLVL2 ULL(0x2)45 #define MPIDR_AFFLVL3 ULL(0x3)208 #define EL_IMPL_NONE ULL(0)725 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))726 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))731 #define TCR_TxSZ_MIN ULL(16)782 #define TCR_TG0_MASK ULL(3)788 #define TCR_TG1_MASK ULL(3)[all …]
23 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)24 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)25 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)26 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)39 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55)40 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)41 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)42 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)52 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14)54 #define CORTEX_A72_L2ACTLR_DISABLE_DVM_CMO_BROADCAST (ULL(1) << 8)[all …]
30 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)31 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)32 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)33 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59)52 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52)53 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)54 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)57 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27)58 #define CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD (ULL(1) << 24)[all …]
20 #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)26 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)33 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)34 #define NEOVERSE_N2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)40 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)41 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)42 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)43 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)49 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)50 #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)[all …]
39 #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24)41 #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)48 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)49 #define NEOVERSE_N1_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)53 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)54 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)55 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)56 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)57 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)58 #define NEOVERSE_N1_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)[all …]
36 #define RAINIER_WS_THR_L2_MASK (ULL(3) << 24)37 #define RAINIER_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51)44 #define RAINIER_CPUACTLR_EL1_BIT_6 (ULL(1) << 6)45 #define RAINIER_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)49 #define RAINIER_CPUACTLR2_EL1_BIT_0 (ULL(1) << 0)50 #define RAINIER_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)51 #define RAINIER_CPUACTLR2_EL1_BIT_11 (ULL(1) << 11)52 #define RAINIER_CPUACTLR2_EL1_BIT_15 (ULL(1) << 15)53 #define RAINIER_CPUACTLR2_EL1_BIT_16 (ULL(1) << 16)54 #define RAINIER_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)[all …]
19 #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)31 #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)32 #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)38 #define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)39 #define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)45 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)46 #define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)47 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)53 #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
24 #define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2 (ULL(3) << 24)25 #define CORTEX_A76_CPUECTLR_EL1_BIT_51 (ULL(1) << 51)32 #define CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION (ULL(1) << 6)34 #define CORTEX_A76_CPUACTLR_EL1_BIT_13 (ULL(1) << 13)38 #define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)40 #define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)44 #define CORTEX_A76_CPUACTLR3_EL1_BIT_10 (ULL(1) << 10)
23 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)24 #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)25 #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)39 #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)40 #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)41 #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)42 #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
21 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)22 #define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)35 #define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30)38 #define CORTEX_A78_ACTLR2_EL1_BIT_0 (ULL(1) << 0)39 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1)40 #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2)41 #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
29 #define CORTEX_A53_ECTLR_SMP_BIT (ULL(1) << 6)32 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)35 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (ULL(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)48 #define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (ULL(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)50 #define CORTEX_A53_CPUACTLR_EL1_RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)52 #define CORTEX_A53_CPUACTLR_EL1_L1RADIS (ULL(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)54 #define CORTEX_A53_CPUACTLR_EL1_DTAH (ULL(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)56 #define CORTEX_A53_CPUACTLR_EL1_L1PCTL (ULL(7) << CORTEX_A53_CPUACTLR_EL1_L1PCTL_SHIFT)
21 #define CORTEX_A55_CPUECTLR_EL1_L1WSCTL (ULL(3) << 25)28 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING (ULL(1) << 24)29 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE (ULL(1) << 31)30 #define CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS (ULL(1) << 49)37 #define CORTEX_A55_CLIDR_EL1_CTYPE3 (ULL(7) << 6)
19 #define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)28 #define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)40 #define CORTEX_X2_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)46 #define CORTEX_X2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)52 #define CORTEX_X2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
29 #define CORTEX_A57_ECTLR_SMP_BIT (ULL(1) << 6)30 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)31 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)32 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)47 #define CORTEX_A57_CPUACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59)50 #define CORTEX_A57_CPUACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54)51 #define CORTEX_A57_CPUACTLR_DIS_OVERREAD (ULL(1) << 52)52 #define CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)53 #define CORTEX_A57_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)56 #define CORTEX_A57_CPUACTLR_DIS_STREAMING (ULL(3) << 27)[all …]
20 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6)21 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38)22 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35)23 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32)35 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56)36 #define CORTEX_A72_CPUACTLR_DIS_LOAD_PASS_STORE (ULL(1) << 55)37 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)38 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)39 #define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
71 #define ARM_DRTM_FUNC_MASK ULL(0x1)74 #define ARM_DRTM_FEAT_ID_MASK ULL(0xff)81 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF)82 #define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1)85 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1)87 #define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1)91 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB)92 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC)93 #define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD)184 #define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0)[all …]
52 #define XN (ULL(1) << 2)54 #define UXN (ULL(1) << 2)55 #define PXN (ULL(1) << 1)56 #define CONT_HINT (ULL(1) << 0)67 #define GP (ULL(1) << 50)127 #define AP2_RO ULL(0x1)128 #define AP2_RW ULL(0x0)131 #define AP1_ACCESS_UNPRIVILEGED ULL(0x1)133 #define AP1_RES1 ULL(0x1)146 #define ATTR_NON_CACHEABLE_INDEX ULL(0x2)[all …]
15 #define PLAT_ARM_BOOT_UART_BASE ULL(0x2A400000)19 #define PLAT_ARM_RUN_UART_BASE ULL(0x1C090000)25 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)26 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000)31 #define PLAT_ARM_FLASH_IMAGE_BASE ULL(0x1A000000)34 #define PLAT_ARM_NVM_BASE ULL(0x1A000000)35 #define PLAT_ARM_NVM_SIZE ULL(0x01000000)46 #define SOC_TRUSTED_NVCTR_BASE ULL(0x7FE70000)159 #define PLAT_ARM_NSRAM_BASE ULL(0x06000000)169 #define MORELLO_DEVICE_BASE ULL(0x08000000)[all …]
39 #define TLK_REQUEST_DONE (0x32000001 | (ULL(1) << 31))40 #define TLK_PREEMPTED (0x32000002 | (ULL(1) << 31))41 #define TLK_ENTRY_DONE (0x32000003 | (ULL(1) << 31))42 #define TLK_VA_TRANSLATE (0x32000004 | (ULL(1) << 31))43 #define TLK_SUSPEND_DONE (0x32000005 | (ULL(1) << 31))44 #define TLK_RESUME_DONE (0x32000006 | (ULL(1) << 31))45 #define TLK_IRQ_DONE (0x32000008 | (ULL(1) << 31))
57 #define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MAX))61 (ULL(1) << (U(64) - TCR_TxSZ_MAX_TTST))62 #define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (U(64) - TCR_TxSZ_MIN))89 (((_virt_addr_space_sz) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \91 : (((_virt_addr_space_sz) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \93 : (((_virt_addr_space_sz) > (ULL(1) << L2_XLAT_ADDRESS_SHIFT)) \
19 return 0ULL; in plat_drtm_get_min_size_normal_world_dce()24 return 0ULL; in plat_drtm_get_imp_def_dlme_region_size()29 return 0ULL; in plat_drtm_get_tcb_hash_features()34 return 0ULL; in plat_drtm_get_tcb_hash_table_size()
Completed in 31 milliseconds