| /arm-trusted-firmware-2.8.0/services/std_svc/spm/spm_mm/ |
| A D | spm_mm_xlat.c | 57 unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) in smc_attr_to_mmap_attr() local
60 if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) { in smc_attr_to_mmap_attr()
62 } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) { in smc_attr_to_mmap_attr()
66 assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); in smc_attr_to_mmap_attr()
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| /arm-trusted-firmware-2.8.0/include/lib/extensions/ |
| A D | ras.h | 45 .access = ERR_ACCESS_SYSREG, \
54 .access = ERR_ACCESS_MEMMAP, \
157 unsigned int access:1; member
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | alt-boot-flows.rst | 8 the highest exception level is required. It allows full, direct access to the
27 configured to permit secure access only. This gives full access to the whole
35 - Little-endian data access;
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| A D | firmware-design.rst | 15 hotplug and idle). Normal world software can access TF-A runtime services via
295 system register access to implemented trace registers.
297 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
314 - Enable the MMU and map the memory it needs to access.
382 access to Floating Point and Advanced SIMD registers by setting the
397 - Enable the MMU and map the memory it needs to access.
577 - Enable the MMU and map the memory it needs to access.
643 EL3, little-endian data access, and all interrupt sources masked:
763 EL3, little-endian data access, and all interrupt sources masked:
825 data access and all interrupt sources masked:
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| /arm-trusted-firmware-2.8.0/tools/fiptool/ |
| A D | win_posix.h | 126 inline int access(const char *path, int mode) in access() function
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| A D | fiptool.c | 859 if (access(argv[0], F_OK) == 0) in update_cmd()
1000 if (access(file, F_OK) != 0 || fflag) { in unpack_cmd()
1114 if (outfile[0] != '\0' && access(outfile, F_OK) == 0 && !fflag) in remove_cmd()
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | secure-partition-manager-mm.rst | 413 instruction access permissions.
419 instruction access permissions.
422 instruction access permissions.
668 - Bits[1:0] : Data access permission
670 - b'00 : No access
671 - b'01 : Read-Write access
673 - b'11 : Read-only access
743 - Bits[1:0] : Data access permission
745 - b'00 : No access
746 - b'01 : Read-Write access
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| A D | granule-protection-tables-design.rst | 13 spaces have been added to control memory access for each state. The PAS access
16 .. list-table:: Security states and PAS access rights
48 level 0 table controls access to a relatively large region in memory (block
103 structures, then the library will check the desired memory access layout for
152 ``pas_region_t`` structures containing the desired memory access layout. The
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| A D | debugfs-design.rst | 73 - This permits direct access to a firmware driver, mainly for test purposes
103 - On concurrent access, a spinlock is implemented in the BL31 service to protect
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| A D | realm-management-extension.rst | 207 -C cluster0.gicv3.cpuintf-mmap-access-level=2 \
225 -C cluster1.gicv3.cpuintf-mmap-access-level=2 \
262 > Test suite 'Invalid memory access'
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| A D | ffa-manifest-binding.rst | 289 - exclusive-access
292 access and ownership of this device's MMIO region.
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/tc/ |
| A D | index.rst | 9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
30 FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/t186/ |
| A D | tegra_mc_def.h | 334 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ argument
341 .override_enable = OVERRIDE_ ## access \
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 14 - **0x2** = SPI direct access
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| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model.rst | 71 | DF3 | | Debug and trace IP on a platform can allow access |
144 | AppDebug | | Physical attacker using debug signals to access |
147 | PhysicalAccess | | Physical attacker having access to external device |
246 that require physical access are unlikely in server environments while
276 | | storage. It is possible for an attacker to access|
408 | Threat | | **An attacker with physical access can execute |
585 | | | Secure and non-secure clients access TF-A services |
670 | | access memory beyond its limit. |
781 | | access sensitive data or execute arbitrary |
786 | | normal world to access sensitive data or even |
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| A D | threat_model_fvp_r.rst | 71 - ID 04: An attacker with physical access can execute arbitrary image by
86 normal world software to access sensitive data or execute arbitrary code.
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| A D | threat_model_el3_spm.rst | 65 | DF7 | External memory access. |
112 - Hardware attacks (non-invasive) requiring a physical access to the device,
333 | | getting access or gaining permissions to a memory |
533 | | access this service.** |
598 | | be able to relinquish the access to shared memory |
636 | Mitigations | Yes. The SPMC tracks ownership and access state |
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| A D | threat_model_spm.rst | 88 | ``DF7`` | External memory access. |
138 - Hardware attacks (non-invasive) requiring a physical access to the device,
381 | | getting access or gaining permissions to a memory |
578 | | access this service.** |
647 | | access to the designated FF-A call. |
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-3.rst | 29 contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
47 permissions separately to data access permissions. All RO normal memory regions
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/ |
| A D | arm-build-options.rst | 13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
17 kernel). Default is true (access to the frame is allowed).
40 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | build-options.rst | 258 - ``ENABLE_FEAT_AMUv1``: Numeric value to enable access to the HAFGRTR_EL2
263 ``ENABLE_FEAT_FGT``, to access the HAFGRTR_EL2 register.
272 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
299 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
307 permission fault for any privileged data access from EL1/EL2 to virtual
325 Barrier) extension allowing access to ``sb`` instruction. ``FEAT_SB`` is an
345 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
363 access their own MPAM registers without trapping into EL3. This option
696 generic UART, which is a subset of the PL011. The driver will not access
1001 bit, to trap access to the RAS ERR and RAS ERX registers from lower ELs.
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | rz-g2.rst | 82 behind using direct shared memory access to BOOT_KIND_BASE _and_
162 - Boot the board in Mini-monitor mode and enable access to the
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| A D | rcar-gen3.rst | 87 behind using direct shared memory access to BOOT_KIND_BASE _and_
189 - Boot the board in Mini-monitor mode and enable access to the
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| A D | rpi4.rst | 62 This part knows how to access the MMC controller and how to parse a FAT
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | security-hardening.rst | 42 Since the Non-secure world has access to the ``PMCR`` register, it can
|