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Searched refs:apupwr_readl (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl.c268 if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) && in apupwr_smc_pll_set_rate()
269 !(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) { in apupwr_smc_pll_set_rate()
273 if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) && in apupwr_smc_pll_set_rate()
274 !(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) { in apupwr_smc_pll_set_rate()
281 if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) && in apupwr_smc_pll_set_rate()
282 !(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) { in apupwr_smc_pll_set_rate()
286 if ((apupwr_readl(acc_set1) & BIT(BIT_CGEN_APU)) && in apupwr_smc_pll_set_rate()
287 !(apupwr_readl(acc_set1) & BIT(BIT_SEL_APU))) { in apupwr_smc_pll_set_rate()
294 if ((apupwr_readl(acc_set0) & BIT(BIT_CGEN_APU)) && in apupwr_smc_pll_set_rate()
295 !(apupwr_readl(acc_set0) & BIT(BIT_SEL_APU))) { in apupwr_smc_pll_set_rate()
A Dapupll.c165 mon_dds = apupwr_readl(fhctl_mon_addr[pll_idx]) & DDS_MASK; in _fhctl_mon_done()
196 val = apupwr_readl(mixed_con1_addr[pll_idx]); in _pll_get_postdiv_reg()
A Dapupwr_clkctl_def.h73 #define apupwr_readl(REG) mmio_read_32((uintptr_t)REG) macro

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