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Searched refs:apupwr_writel (Results 1 – 3 of 3) sorted by relevance

/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl.c76 apupwr_writel(init_acc_cfg[i].val, in apupwr_smc_acc_init_all()
146 apupwr_writel(BIT(BIT_SEL_PARK), acc_set); in apupwr_smc_acc_set_parent()
147 apupwr_writel(BIT(BIT_SEL_F26M), acc_clr); in apupwr_smc_acc_set_parent()
152 apupwr_writel(BIT(BIT_SEL_APU), acc_clr); in apupwr_smc_acc_set_parent()
159 apupwr_writel(BIT(BIT_SEL_APU), acc_set); in apupwr_smc_acc_set_parent()
167 apupwr_writel(BIT(BIT_SEL_PARK), acc_clr); in apupwr_smc_acc_set_parent()
168 apupwr_writel(BIT(BIT_SEL_F26M), acc_clr); in apupwr_smc_acc_set_parent()
170 apupwr_writel(BIT(BIT_CGEN_SOC), acc_set); in apupwr_smc_acc_set_parent()
173 apupwr_writel(BIT(BIT_SEL_APU), acc_clr); in apupwr_smc_acc_set_parent()
182 apupwr_writel(BIT(BIT_SEL_F26M), acc_set); in apupwr_smc_acc_set_parent()
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A Dapupll.c538 apupwr_writel(pd, mixed_con1_addr[pll_idx]); in anpu_pll_set_rate()
544 apupwr_writel(dds, fhctl_dds_addr[pll_idx]); in anpu_pll_set_rate()
556 apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]); in anpu_pll_set_rate()
558 apupwr_writel(dds, fhctl_dvfs_addr[pll_idx]); in anpu_pll_set_rate()
A Dapupwr_clkctl_def.h71 #define apupwr_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL) macro

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