| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | romlib-design.rst | 1 Library at ROM
4 This document provides an overview of the "library at ROM" implementation in
13 are placed in ROM. The capabilities of the "library at ROM" are:
37 function -- Name of the function to be placed in library at ROM
63 BL image --> wrapper function --> jump table entry --> library at ROM
72 global variables defined by the functions inside "library at ROM".
102 Patching of functions in library at ROM
108 "library at ROM" version of this function.
117 Using library at ROM will modify the memory layout of the BL images:
132 Build library at ROM
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | mt8186.rst | 6 Cortex-A76 can operate at up to 2.05 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| A D | mt8192.rst | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2 GHz.
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| A D | mt8195.rst | 6 Cortex-A76 can operate at up to 2.2 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| A D | mt8188.rst | 6 Cortex-A78 can operate at up to 2.6 GHz.
7 Cortex-A55 can operate at up to 2.0 GHz.
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| A D | poplar.rst | 12 video at 60 frames per second.
116 LOADER: CPU0 executes at 0x000ce000
124 INFO: Loading image id=1 at address 0xe9000
125 INFO: Image id=1 loaded at address 0xe9000, size = 0x5008
132 INFO: Loading image id=3 at address 0x129000
133 INFO: Image id=3 loaded at address 0x129000, size = 0x8038
135 INFO: Loading image id=5 at address 0x37000000
136 INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17
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| A D | qti.rst | 40 QTISELIB for SC7180 is available at
42 QTISELIB for SC7280 is available at
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| A D | mt8183.rst | 6 Both clusters can operate at up to 2 GHz.
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| A D | intel-stratix10.rst | 78 INFO: Loading image id=3 at address 0xffe1c000
81 INFO: Loading image id=5 at address 0x50000
94 UEFI firmware (version 1.0 built at 11:26:18 on Nov 7 2018)
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| /arm-trusted-firmware-2.8.0/docs/perf/ |
| A D | performance-monitoring-unit.rst | 18 The PMU makes 32 counters available at all privilege levels:
50 ``PMCR`` registers. These can be accessed at all privilege levels.
79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
84 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
91 - If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
98 at Secure EL2.
104 - If equal to the ``P`` bit it enables the associated ``PMEVCNTR<n>`` at
121 In other words, the counter will not increment at any privilege level or
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/fvp_r/ |
| A D | index.rst | 9 - MPU Support only at EL2
10 - MPU or MMU Support at EL0/EL1
14 Further information on v8-R64 FVP is available at `info <https://developer.arm.com/documentation/dd…
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/morello/ |
| A D | index.rst | 5 The platform port present at `site <https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git>`_
10 Further information on Morello Platform is available at `info <https://developer.arm.com/architectu…
16 execution. SCP_BL2 powers up the AP which starts execution at AP_BL31. The AP
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | arm_fpga.dts | 8 * populated accordingly at runtime.
34 /* /cpus node will be added by BL31 at runtime. */
54 /* This node will be removed at runtime on cores without SPE. */
97 /* The GICR size will be adjusted at runtime to match the cores. */
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| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/fdts/ |
| A D | fvp_fw_config.dts | 29 * Load SoC and TOS firmware configs at the base of
32 * is loaded at base of DRAM.
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| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/ |
| A D | build.rst | 22 For example: if U-Boot project (and its images) is located at ``~/project/u-boot``,
233 - CPU_600_DDR_600 - CPU at 600 MHz, DDR at 600 MHz
234 - CPU_800_DDR_800 - CPU at 800 MHz, DDR at 800 MHz
235 - CPU_1000_DDR_800 - CPU at 1000 MHz, DDR at 800 MHz
236 - CPU_1200_DDR_750 - CPU at 1200 MHz, DDR at 750 MHz
260 Image needs to be stored at disk LBA 0 or at disk partition with
292 CZ.NIC's Armada 3720 Secure Firmware is available at website:
342 the image has the preset CPU at 1000 MHz, preset DDR3 at 800 MHz, the DDR topology of DDR4 2CS,
452 (3) Armada3700 tools available at the following repository
457 (4) Crypto++ library available at the following repository:
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| /arm-trusted-firmware-2.8.0/docs/components/fconf/ |
| A D | amu-bindings.rst | 65 | ``enable-at-el3`` | O | ``<empty>`` | The presence of this property |
90 enable-at-el3;
96 enable-at-el3;
107 enable-at-el3;
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| /arm-trusted-firmware-2.8.0/services/spd/tlkd/ |
| A D | tlkd_common.c | 38 int at = type & AT_MASK; in tlkd_va_translate() local
39 switch (at) { in tlkd_va_translate()
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | alt-boot-flows.rst | 7 On a pre-production system, the ability to execute arbitrary, bare-metal code at
52 - The EL3 payload needs to be loaded in volatile memory (e.g. DRAM) at
56 used. The infinite loop that it introduces in BL1 stops execution at the right
71 is complete, TF-A simply jumps to a BL33 base address provided at build time.
75 without a BL33 and prepare to jump to a BL33 image loaded at address
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| /arm-trusted-firmware-2.8.0/docs/components/spd/ |
| A D | optee-dispatcher.rst | 6 To build and execute OP-TEE follow the instructions at
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| /arm-trusted-firmware-2.8.0/include/arch/aarch64/ |
| A D | arch_helpers.h | 213 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
214 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
215 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
216 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
217 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r)
218 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r)
219 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r)
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| /arm-trusted-firmware-2.8.0/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 20 be auto-detected at runtime.
23 across the various images, this is detected at runtime by BL31.
45 so it must describe at least the UART and a GICv3 interrupt controller.
87 components at their respective load addresses. In addition to this file
88 you need at least a BL33 payload (typically a Linux kernel image), optionally
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-6.rst | 55 is not effective at invalidating the branch predictor on Cortex-A73/Cortex-A75.
75 disable/enable" and "BPIALL at AArch32 Secure-EL1" workarounds described above.
80 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
97 | ``PSCI_VERSION`` with "BPIALL at AArch32 Secure-EL1" | 1276 |
99 | ``SMCCC_ARCH_WORKAROUND_1`` with "BPIALL at AArch32 Secure-EL1" | 770 |
104 performance and code size overhead. Platforms can choose to disable them at
112 effective at invalidating the branch predictor on Cortex-A15. For that CPU, set
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| A D | security-advisory-tfv-3.rst | 5 | Title | RO memory is always executable at AArch64 Secure EL1 |
15 | Affected | executing at AArch64 Secure EL1 |
34 This feature does not work correctly for AArch64 images executing at Secure EL1.
62 permissions but always leaves the memory as executable at Secure EL1.
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| /arm-trusted-firmware-2.8.0/lib/locks/exclusive/aarch64/ |
| A D | spinlock.S | 14 #error USE_SPINLOCK_CAS option requires at least an ARMv8.1 platform
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| /arm-trusted-firmware-2.8.0/ |
| A D | .editorconfig | 51 # "Get a decent editor and don't leave whitespace at the end of lines."
53 # "Do not leave trailing whitespace at the ends of lines."
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