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/arm-trusted-firmware-2.8.0/drivers/arm/gic/v3/
A Dgicdv3_helpers.c44 GICD_SET_BIT(IGROUP, base, id); in gicd_set_igroupr()
49 GICD_CLR_BIT(IGROUP, base, id); in gicd_clr_igroupr()
63 GICD_SET_BIT(IGRPMOD, base, id); in gicd_set_igrpmodr()
68 GICD_CLR_BIT(IGRPMOD, base, id); in gicd_clr_igrpmodr()
77 GICD_WRITE_BIT(ICENABLE, base, id); in gicd_set_icenabler()
86 GICD_WRITE_BIT(ICPEND, base, id); in gicd_set_icpendr()
118 GICD_WRITE_BIT(ISPEND, base, id); in gicd_set_ispendr()
140 return GICD_READ(ICFG, base, id); in gicd_read_icfgr()
145 GICD_WRITE(ICFG, base, id, val); in gicd_write_icfgr()
238 return GICD_READ(NSAC, base, id); in gicd_read_nsacr()
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A Dgicv3_private.h69 #define GICD_READ(REG, base, id) \ argument
72 #define GICD_READ_64(REG, base, id) \ argument
78 #define GICD_WRITE(REG, base, id, val) \ argument
89 #define GICD_GET_BIT(REG, base, id) \ argument
94 #define GICD_SET_BIT(REG, base, id) \ argument
99 #define GICD_CLR_BIT(REG, base, id) \ argument
133 #define GICR_READ(REG, base, id) \ argument
291 gicd_write_ctlr(base, gicd_read_ctlr(base) & ~bitmap); in gicd_clr_ctlr()
293 gicd_wait_for_pending_write(base); in gicd_clr_ctlr()
301 gicd_write_ctlr(base, gicd_read_ctlr(base) | bitmap); in gicd_set_ctlr()
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A Dgic600ae_fmu_helpers.c19 #define GIC_FMU_WRITE_32(base, reg, val) \ argument
25 mmio_write_32(base + GICFMU_KEY, 0xBE); \
27 mmio_write_32((base) + (reg), (val)); \
37 mmio_write_32(base + GICFMU_KEY, 0xBE); \
69 wait_until_fmu_is_idle(base); \
71 GIC_FMU_WRITE_32(base, reg, val); \
73 wait_until_fmu_is_idle(base); \
79 wait_until_fmu_is_idle(base); \
81 GIC_FMU_WRITE_64(base, reg, n, val); \
83 wait_until_fmu_is_idle(base); \
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A Dgicrv3_helpers.c26 return GICR_READ(IPRIORITY, base, id); in gicr_read_ipriorityr()
31 GICR_WRITE(IPRIORITY, base, id, val); in gicr_write_ipriorityr()
49 return GICR_GET_BIT(IGROUP, base, id); in gicr_get_igroupr()
54 GICR_SET_BIT(IGROUP, base, id); in gicr_set_igroupr()
59 GICR_CLR_BIT(IGROUP, base, id); in gicr_clr_igroupr()
73 GICR_SET_BIT(IGRPMOD, base, id); in gicr_set_igrpmodr()
78 GICR_CLR_BIT(IGRPMOD, base, id); in gicr_clr_igrpmodr()
87 GICR_WRITE_BIT(ISENABLE, base, id); in gicr_set_isenabler()
96 GICR_WRITE_BIT(ICENABLE, base, id); in gicr_set_icenabler()
114 GICR_WRITE_BIT(ICPEND, base, id); in gicr_set_icpendr()
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/arm-trusted-firmware-2.8.0/drivers/arm/gic/common/
A Dgic_common_private.h18 static inline unsigned int gicd_read_ctlr(uintptr_t base) in gicd_read_ctlr() argument
20 return mmio_read_32(base + GICD_CTLR); in gicd_read_ctlr()
23 static inline unsigned int gicd_read_typer(uintptr_t base) in gicd_read_typer() argument
25 return mmio_read_32(base + GICD_TYPER); in gicd_read_typer()
28 static inline unsigned int gicd_read_iidr(uintptr_t base) in gicd_read_iidr() argument
30 return mmio_read_32(base + GICD_IIDR); in gicd_read_iidr()
35 mmio_write_32(base + GICD_CTLR, val); in gicd_write_ctlr()
77 void gicd_set_igroupr(uintptr_t base, unsigned int id);
78 void gicd_clr_igroupr(uintptr_t base, unsigned int id);
81 void gicd_set_ispendr(uintptr_t base, unsigned int id);
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A Dgic_common.c27 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
115 return mmio_read_32(base + GICD_ICFGR + (n << 2)); in gicd_read_icfgr()
126 return mmio_read_32(base + GICD_NSACR + (n << 2)); in gicd_read_nsacr()
276 gicd_write_isenabler(base, id, (1U << bit_num)); in gicd_set_isenabler()
283 gicd_write_icenabler(base, id, (1U << bit_num)); in gicd_set_icenabler()
290 gicd_write_ispendr(base, id, (1U << bit_num)); in gicd_set_ispendr()
297 gicd_write_icpendr(base, id, (1U << bit_num)); in gicd_set_icpendr()
312 gicd_write_isactiver(base, id, (1U << bit_num)); in gicd_set_isactiver()
326 mmio_write_8(base + GICD_IPRIORITYR + id, val); in gicd_set_ipriorityr()
335 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr()
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/arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/
A Dgicv2_private.h53 mmio_write_32(base + GICD_SGIR, val); in gicd_write_sgir()
62 return mmio_read_32(base + GICC_CTLR); in gicc_read_ctlr()
67 return mmio_read_32(base + GICC_PMR); in gicc_read_pmr()
72 return mmio_read_32(base + GICC_BPR); in gicc_read_BPR()
77 return mmio_read_32(base + GICC_IAR); in gicc_read_IAR()
97 return mmio_read_32(base + GICC_DIR); in gicc_read_dir()
107 return mmio_read_32(base + GICC_RPR); in gicc_read_rpr()
121 mmio_write_32(base + GICC_PMR, val); in gicc_write_pmr()
126 mmio_write_32(base + GICC_BPR, val); in gicc_write_BPR()
132 mmio_write_32(base + GICC_IAR, val); in gicc_write_IAR()
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A Dgicdv2_helpers.c25 return mmio_read_32(base + GICD_IGROUPR + (n << 2)); in gicd_read_igroupr()
113 return mmio_read_32(base + GICD_ICFGR + (n << 2)); in gicd_read_icfgr()
124 return mmio_read_32(base + GICD_NSACR + (n << 2)); in gicd_read_nsacr()
274 gicd_write_isenabler(base, id, (1U << bit_num)); in gicd_set_isenabler()
281 gicd_write_icenabler(base, id, (1U << bit_num)); in gicd_set_icenabler()
288 gicd_write_ispendr(base, id, (1U << bit_num)); in gicd_set_ispendr()
295 gicd_write_icpendr(base, id, (1U << bit_num)); in gicd_set_icpendr()
310 gicd_write_isactiver(base, id, (1U << bit_num)); in gicd_set_isactiver()
324 mmio_write_8(base + GICD_IPRIORITYR + id, val); in gicd_set_ipriorityr()
333 uint32_t reg_val = gicd_read_icfgr(base, id); in gicd_set_icfgr()
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/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/drivers/pwrc/
A Dhisi_pwrc.h16 #define SOC_CRGPERIPH_A53_PDCEN_ADDR(base) ((base) + (0x260)) argument
17 #define SOC_CRGPERIPH_MAIA_PDCEN_ADDR(base) ((base) + (0x300)) argument
19 #define SOC_PCTRL_RESOURCE0_LOCK_ADDR(base) ((base) + (0x400)) argument
20 #define SOC_PCTRL_RESOURCE0_UNLOCK_ADDR(base) ((base) + (0x404)) argument
21 #define SOC_PCTRL_RESOURCE0_LOCK_ST_ADDR(base) ((base) + (0x408)) argument
22 #define SOC_PCTRL_RESOURCE1_LOCK_ADDR(base) ((base) + (0x40C)) argument
23 #define SOC_PCTRL_RESOURCE1_UNLOCK_ADDR(base) ((base) + (0x410)) argument
25 #define SOC_PCTRL_RESOURCE2_LOCK_ADDR(base) ((base) + (0x418)) argument
27 #define SOC_SCTRL_SCBAKDATA3_ADDR(base) ((base) + (0x418)) argument
28 #define SOC_SCTRL_SCBAKDATA8_ADDR(base) ((base) + (0x42C)) argument
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/arm-trusted-firmware-2.8.0/drivers/arm/sp805/
A Dsp805.c16 mmio_write_32(base + SP805_WDOG_LOAD_OFF, value); in sp805_write_wdog_load()
21 mmio_write_32(base + SP805_WDOG_CTR_OFF, value); in sp805_write_wdog_ctrl()
26 mmio_write_32(base + SP805_WDOG_LOCK_OFF, value); in sp805_write_wdog_lock()
34 sp805_write_wdog_load(base, ticks); in sp805_start()
37 sp805_write_wdog_lock(base, 0U); in sp805_start()
40 void sp805_stop(uintptr_t base) in sp805_stop() argument
42 sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); in sp805_stop()
43 sp805_write_wdog_ctrl(base, 0U); in sp805_stop()
48 sp805_write_wdog_lock(base, WDOG_UNLOCK_KEY); in sp805_refresh()
49 sp805_write_wdog_load(base, ticks); in sp805_refresh()
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/arm-trusted-firmware-2.8.0/plat/mediatek/drivers/uart/
A Duart.c21 unsigned long base; in mt_uart_restore() local
28 base = uart->base; in mt_uart_restore()
30 mmio_write_32(UART_LCR(base), UART_LCR_MODE_B); in mt_uart_restore()
39 mmio_write_32(UART_LCR(base), in mt_uart_restore()
44 mmio_write_32(UART_SAMPLE_COUNT(base), in mt_uart_restore()
46 mmio_write_32(UART_SAMPLE_POINT(base), in mt_uart_restore()
62 unsigned long base; in mt_uart_save() local
68 base = uart_base_addr[uart_idx]; in mt_uart_save()
81 mmio_write_32(UART_LCR(base), in mt_uart_save()
87 UART_SAMPLE_COUNT(base)); in mt_uart_save()
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/arm-trusted-firmware-2.8.0/drivers/arm/tzc/
A Dtzc380.c15 uintptr_t base; member
24 return mmio_read_32(base + TZC380_CONFIGURATION_OFF); in tzc380_read_build_config()
29 mmio_write_32(base + ACTION_OFF, action); in tzc380_write_action()
35 mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val); in tzc380_write_region_base_low()
50 void tzc380_init(uintptr_t base) in tzc380_init() argument
54 assert(base != 0U); in tzc380_init()
55 tzc380.base = base; in tzc380_init()
58 tzc_build = tzc380_read_build_config(tzc380.base); in tzc380_init()
85 assert(tzc380.base != 0U); in tzc380_configure_region()
96 assert(tzc380.base != 0U); in tzc380_set_action()
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A Dtzc400.c34 uintptr_t base; member
151 open_status = get_gate_keeper_os(base); in _tzc400_get_gate_keeper()
181 assert(tzc400.base != 0U); in tzc400_set_action()
187 void tzc400_init(uintptr_t base) in tzc400_init() argument
194 assert(base != 0U); in tzc400_init()
195 tzc400.base = base; in tzc400_init()
224 assert(tzc400.base != 0U); in tzc400_configure_region0()
247 assert(tzc400.base != 0U); in tzc400_configure_region()
289 assert(tzc400.base != 0U); in tzc400_enable_filters()
323 assert(tzc400.base != 0U); in tzc400_disable_filters()
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A Dtzc_common_private.h17 uintptr_t base, \
26 uintptr_t base, \
30 mmio_write_32(base + \
36 mmio_write_32(base + \
46 uintptr_t base, \
50 mmio_write_32(base + \
56 mmio_write_32(base + \
66 uintptr_t base, \
70 mmio_write_32(base + \
80 uintptr_t base, \
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/arm-trusted-firmware-2.8.0/drivers/brcm/
A Docotp.c59 uint32_t base; member
64 .base = OTPC_MODE_REG,
69 uint32_t base; member
124 set_command(priv->base, OTPC_CMD_ECC); in bcm_otpc_ecc()
132 set_start_bit(priv->base); in bcm_otpc_ecc()
138 reset_start_bit(priv->base); in bcm_otpc_ecc()
167 set_start_bit(priv->base); in bcm_otpc_read()
175 *buf++ = mmio_read_32(priv->base + in bcm_otpc_read()
180 reset_start_bit(priv->base); in bcm_otpc_read()
191 priv->base = ocotp_cfg.base; in bcm_otpc_init()
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/arm-trusted-firmware-2.8.0/plat/socionext/uniphier/
A Duniphier_console_setup.c49 uintptr_t base, end; in uniphier_console_get_base() local
53 base = uniphier_uart_base[soc]; in uniphier_console_get_base()
56 while (base < end) { in uniphier_console_get_base()
59 return base; in uniphier_console_get_base()
60 base += UNIPHIER_UART_OFFSET; in uniphier_console_get_base()
69 mmio_write_32(base + UNIPHIER_UART_LCR_MCR, in uniphier_console_init()
75 uintptr_t base; in uniphier_console_setup() local
77 base = uniphier_console_get_base(soc); in uniphier_console_setup()
78 if (!base) in uniphier_console_setup()
81 uniphier_console.base = base; in uniphier_console_setup()
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/arm-trusted-firmware-2.8.0/plat/imx/common/sci/
A Dimx8_mu.c11 void MU_Resume(uint32_t base) in MU_Resume() argument
15 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Resume()
19 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_Resume()
23 MU_EnableRxFullInt(base, i); in MU_Resume()
28 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableRxFullInt()
32 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableRxFullInt()
37 uint32_t reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_EnableGeneralInt()
41 mmio_write_32(base + MU_ACR_OFFSET1, reg); in MU_EnableGeneralInt()
64 void MU_Init(uint32_t base) in MU_Init() argument
68 reg = mmio_read_32(base + MU_ACR_OFFSET1); in MU_Init()
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A Dipc.c36 uint32_t base = id; in sc_ipc_open() local
40 if ((ipc == NULL) || (base == 0)) in sc_ipc_open()
46 MU_Init(base); in sc_ipc_open()
50 MU_EnableRxFullInt(base, i); in sc_ipc_open()
61 uint32_t base = ipc; in sc_ipc_close() local
63 if (base != 0) in sc_ipc_close()
64 MU_Init(base); in sc_ipc_close()
69 uint32_t base = ipc; in sc_ipc_read() local
74 if ((base == 0) || (msg == NULL)) in sc_ipc_read()
98 uint32_t base = ipc; in sc_ipc_write() local
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/arm-trusted-firmware-2.8.0/drivers/marvell/mochi/
A Dcp110_setup.c180 static void cp110_pcie_clk_cfg(uintptr_t base) in cp110_pcie_clk_cfg() argument
238 mmio_write_32(base + stream_id_reg[i], in cp110_stream_id_init()
253 static void cp110_axi_attr_init(uintptr_t base) in cp110_axi_attr_init() argument
318 void cp110_amb_init(uintptr_t base) in cp110_amb_init() argument
331 static void cp110_rtc_init(uintptr_t base) in cp110_rtc_init() argument
351 if ((mmio_read_32(base + MVEBU_RTC_CCR_REG) & in cp110_rtc_init()
358 mmio_write_32(base + MVEBU_RTC_STATUS_REG, in cp110_rtc_init()
370 mmio_write_32(base + MVEBU_RTC_CCR_REG, in cp110_rtc_init()
374 mmio_write_32(base + MVEBU_RTC_STATUS_REG, in cp110_rtc_init()
388 init_amb_adec(base); in cp110_amb_adec_init()
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/arm-trusted-firmware-2.8.0/plat/marvell/armada/a8k/common/mss/
A Dmss_defs.h11 #define MSS_DMA_SRCBR(base) (base + 0xC0) argument
12 #define MSS_DMA_DSTBR(base) (base + 0xC4) argument
13 #define MSS_DMA_CTRLR(base) (base + 0xC8) argument
14 #define MSS_M3_RSTCR(base) (base + 0xFC) argument
/arm-trusted-firmware-2.8.0/plat/rpi/rpi4/
A Drpi4_pci_svc.c48 uint64_t base; in pci_segment_lib_get_base() local
52 base = PCIE_REG_BASE; in pci_segment_lib_get_base()
65 base += PCIE_EXT_CFG_DATA; in pci_segment_lib_get_base()
87 return base + offset; in pci_segment_lib_get_base()
114 uint64_t base; in pci_read_config() local
120 *val = base; in pci_read_config()
124 *val = mmio_read_8(base); in pci_read_config()
163 uint64_t base; in pci_write_config() local
171 mmio_write_8(base, val); in pci_write_config()
174 mmio_write_16(base, val); in pci_write_config()
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/arm-trusted-firmware-2.8.0/drivers/st/crypto/
A Dstm32_saes.c175 pdata->base = (uintptr_t)info.base; in stm32_saes_parse_fdt()
314 clear_computation_completed(ctx->base); in saes_prepare_key()
436 ctx->base = saes_pdata.base; in stm32_saes_init()
596 clear_computation_completed(ctx->base); in stm32_saes_update_assodata()
626 clear_computation_completed(ctx->base); in stm32_saes_update_assodata()
713 clear_computation_completed(ctx->base); in stm32_saes_update_load()
744 clear_computation_completed(ctx->base); in stm32_saes_update_load()
787 mmio_write_32(ctx->base + _SAES_DINR, 0); in stm32_saes_final()
789 mmio_write_32(ctx->base + _SAES_DINR, 0); in stm32_saes_final()
803 clear_computation_completed(ctx->base); in stm32_saes_final()
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/arm-trusted-firmware-2.8.0/drivers/arm/sbsa/
A Dsbsa.c13 void sbsa_watchdog_offset_reg_write(uintptr_t base, uint64_t value) in sbsa_watchdog_offset_reg_write() argument
16 mmio_write_32(base + SBSA_WDOG_WOR_LOW_OFFSET, in sbsa_watchdog_offset_reg_write()
18 mmio_write_32(base + SBSA_WDOG_WOR_HIGH_OFFSET, (uint32_t)(value >> 32)); in sbsa_watchdog_offset_reg_write()
26 void sbsa_wdog_start(uintptr_t base, uint64_t ms) in sbsa_wdog_start() argument
34 sbsa_watchdog_offset_reg_write(base, offset_reg_value); in sbsa_wdog_start()
35 mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, SBSA_WDOG_WCS_EN); in sbsa_wdog_start()
39 void sbsa_wdog_stop(uintptr_t base) in sbsa_wdog_stop() argument
41 mmio_write_32(base + SBSA_WDOG_WCS_OFFSET, (0x0)); in sbsa_wdog_stop()
/arm-trusted-firmware-2.8.0/drivers/arm/scu/
A Dscu.c17 void enable_snoop_ctrl_unit(uintptr_t base) in enable_snoop_ctrl_unit() argument
23 assert(base != 0U); in enable_snoop_ctrl_unit()
24 scu_ctrl = mmio_read_32(base + SCU_CTRL_REG); in enable_snoop_ctrl_unit()
32 mmio_write_32(base + SCU_CTRL_REG, scu_ctrl); in enable_snoop_ctrl_unit()
46 uint32_t read_snoop_ctrl_unit_cfg(uintptr_t base) in read_snoop_ctrl_unit_cfg() argument
48 assert(base != 0U); in read_snoop_ctrl_unit_cfg()
50 return mmio_read_32(base + SCU_CFG_REG); in read_snoop_ctrl_unit_cfg()
/arm-trusted-firmware-2.8.0/include/drivers/arm/
A Dgic600ae_fmu.h133 uint64_t gic_fmu_read_errgsr(uintptr_t base);
134 uint32_t gic_fmu_read_pingctlr(uintptr_t base);
135 uint32_t gic_fmu_read_pingnow(uintptr_t base);
136 uint64_t gic_fmu_read_pingmask(uintptr_t base);
137 uint32_t gic_fmu_read_status(uintptr_t base);
138 uint32_t gic_fmu_read_erridr(uintptr_t base);
141 void gic_fmu_write_pingctlr(uintptr_t base, uint32_t val);
142 void gic_fmu_write_pingnow(uintptr_t base, uint32_t val);
143 void gic_fmu_write_smen(uintptr_t base, uint32_t val);
144 void gic_fmu_write_sminjerr(uintptr_t base, uint32_t val);
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