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/arm-trusted-firmware-2.8.0/fdts/
A Dstm32mp151.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
42 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
75 #size-cells = <1>;
[all …]
A Dmorello-soc.dts18 #address-cells = <2>;
19 #size-cells = <2>;
29 #address-cells = <2>;
30 #size-cells = <0>;
83 #iommu-cells = <1>;
94 #size-cells = <2>;
130 #size-cells = <2>;
244 #msi-cells = <1>;
251 #msi-cells = <1>;
258 #msi-cells = <1>;
[all …]
A Dstm32mp131.dtsi11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
55 #clock-cells = <0>;
76 #address-cells = <1>;
[all …]
A Dn1sdp.dtsi10 #address-cells = <2>;
11 #size-cells = <2>;
14 #address-cells = <2>;
15 #size-cells = <0>;
72 #clock-cells = <0>;
79 #clock-cells = <0>;
87 #size-cells = <2>;
94 #size-cells = <2>;
105 #msi-cells = <1>;
112 #msi-cells = <1>;
[all …]
A Dcorstone700.dtsi12 #address-cells = <1>;
13 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
37 #address-cells = <0>;
52 #clock-cells = <0>;
60 #clock-cells = <0>;
68 #clock-cells = <0>;
103 #size-cells = <1>;
121 #mbox-cells = <1>;
[all …]
A Dfvp-ve-Cortex-A7x1.dts17 #address-cells = <2>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
37 #address-cells = <2>;
38 #size-cells = <1>;
52 #interrupt-cells = <3>;
53 #address-cells = <0>;
65 #clock-cells = <0>;
80 #interrupt-cells = <1>;
A Dmorello.dtsi13 #address-cells = <2>;
14 #size-cells = <2>;
22 #address-cells = <2>;
23 #interrupt-cells = <3>;
24 #size-cells = <2>;
59 #mbox-cells = <2>;
69 #address-cells = <1>;
70 #size-cells = <1>;
86 #clock-cells = <0>;
93 #clock-cells = <0>;
A Dfvp-ve-Cortex-A5x1.dts17 #address-cells = <2>;
18 #size-cells = <1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
38 #address-cells = <2>;
39 #size-cells = <1>;
73 #address-cells = <0>;
85 #clock-cells = <0>;
94 #clock-cells = <0>;
103 #clock-cells = <0>;
[all …]
A Dfvp-foundation-gicv3-psci.dts26 #address-cells = <2>;
27 #size-cells = <2>;
50 #address-cells = <2>;
51 #size-cells = <0>;
92 #interrupt-cells = <3>;
93 #address-cells = <2>;
94 #size-cells = <2>;
128 #address-cells = <2>;
129 #size-cells = <2>;
149 #address-cells = <2>;
[all …]
A Dstm32mp157c-ev1.dts34 #address-cells = <1>;
35 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
53 #address-cells = <1>;
54 #size-cells = <1>;
A Dtc.dts12 #address-cells = <2>;
13 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
84 #size-cells = <0>;
206 #size-cells = <2>;
232 #size-cells = <1>;
246 #mbox-cells = <2>;
258 #mbox-cells = <2>;
276 #size-cells = <0>;
[all …]
A Da5ds.dts13 #address-cells = <1>;
14 #size-cells = <1>;
23 #address-cells = <1>;
24 #size-cells = <0>;
69 #clock-cells = <0>;
76 #clock-cells = <0>;
83 #clock-cells = <0>;
99 #interrupt-cells = <3>;
100 #address-cells = <0>;
127 #address-cells = <1>;
[all …]
A Dfvp-foundation-gicv2-psci.dts26 #address-cells = <2>;
27 #size-cells = <2>;
50 #address-cells = <2>;
51 #size-cells = <0>;
92 #interrupt-cells = <3>;
93 #address-cells = <0>;
119 #address-cells = <2>;
120 #size-cells = <2>;
140 #address-cells = <2>;
141 #size-cells = <1>;
A Dfvp-base-gicv3.dtsi12 #interrupt-cells = <3>;
13 #address-cells = <1>;
14 #size-cells = <1>;
27 #msi-cells = <1>;
A Darm_fpga.dts19 #address-cells = <2>;
20 #size-cells = <2>;
69 #clock-cells = <0>;
76 #clock-cells = <0>;
91 #address-cells = <2>;
92 #interrupt-cells = <3>;
93 #size-cells = <2>;
104 #msi-cells = <1>;
A Dmorello-fvp.dts18 #address-cells = <2>;
19 #size-cells = <2>;
29 #address-cells = <2>;
30 #size-cells = <0>;
145 #address-cells = <1>;
146 #size-cells = <0>;
150 #clock-cells = <1>;
157 #clock-cells = <0>;
A Dfvp-foundation-motherboard.dtsi10 #address-cells = <2>; /* SMB chipselect number and offset */
11 #size-cells = <1>;
22 #clock-cells = <0>;
29 #clock-cells = <0>;
36 #clock-cells = <0>;
43 #address-cells = <1>;
44 #size-cells = <1>;
51 #gpio-cells = <2>;
59 #clock-cells = <1>;
A Drtsm_ve-motherboard.dtsi15 #clock-cells = <0>;
22 #clock-cells = <0>;
29 #clock-cells = <0>;
51 #clock-cells = <0>;
83 #address-cells = <2>;
84 #size-cells = <1>;
90 #size-cells = <1>;
113 #address-cells = <1>;
114 #size-cells = <1>;
121 #gpio-cells = <2>;
[all …]
A Dn1sdp-multi-chip.dts65 #iommu-cells = <1>;
75 #address-cells = <3>;
76 #size-cells = <2>;
81 #interrupt-cells = <1>;
104 #msi-cells = <1>;
111 #msi-cells = <1>;
A Dfvp-base-gicv2.dtsi12 #interrupt-cells = <3>;
13 #address-cells = <1>;
A Dn1sdp-single-chip.dts35 #clock-cells = <0>;
42 #clock-cells = <0>;
64 #address-cells = <1>;
65 #size-cells = <0>;
/arm-trusted-firmware-2.8.0/plat/arm/board/fvp/fdts/
A Dfvp_spmc_optee_sp_manifest.dts17 #address-cells = <2>;
18 #size-cells = <1>;
42 #address-cells = <0x2>;
43 #size-cells = <0x0>;
A Dfvp_spmc_manifest.dts17 #address-cells = <2>;
18 #size-cells = <1>;
63 #address-cells = <0x2>;
64 #size-cells = <0x0>;
/arm-trusted-firmware-2.8.0/docs/components/fconf/
A Damu-bindings.rst43 | ``#address-cells`` | R | ``<u32>`` | Value shall be 1. Specifies that |
48 | ``#size-cells`` | R | ``<u32>`` | Value shall be 0. Specifies that |
79 #address-cells = <2>;
80 #size-cells = <0>;
84 #address-cells = <1>;
85 #size-cells = <0>;
101 #address-cells = <1>;
102 #size-cells = <0>;
/arm-trusted-firmware-2.8.0/plat/arm/board/n1sdp/fdts/
A Dn1sdp_optee_spmc_manifest.dts10 #address-cells = <2>;
11 #size-cells = <1>;

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