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Searched refs:channel (Results 1 – 15 of 15) sorted by relevance

/arm-trusted-firmware-2.8.0/lib/debugfs/
A Ddev.c48 return channel; in create_new_channel()
70 return (channel == NULL) ? -1 : (channel - fdset); in channel_to_fd()
206 if ((channel->index == index) && (channel->qid == qid)) { in mount_point_to_channel()
251 return channel; in devattach()
306 if (devtab[channel->index]->walk(channel, elem) < 0) { in path_to_channel()
311 mnt = mount_point_to_channel(channel->index, channel->qid); in path_to_channel()
597 r = devtab[channel->index]->stat(channel, path, dir); in stat()
625 return devtab[channel->index]->read(channel, buf, n); in read()
650 return devtab[channel->index]->write(channel, buf, n); in write()
670 return devtab[channel->index]->seek(channel, off, whence); in seek()
[all …]
A Ddevroot.c30 static int rootgen(chan_t *channel, const dirtab_t *tab, int ntab, in rootgen() argument
33 switch (channel->qid & ~CHDIR) { in rootgen()
50 return devgen(channel, tab, ntab, n, dir); in rootgen()
53 static int rootwalk(chan_t *channel, const char *name) in rootwalk() argument
55 return devwalk(channel, name, NULL, 0, rootgen); in rootwalk()
61 static int rootread(chan_t *channel, void *buf, int size) in rootread() argument
66 if ((channel->qid & CHDIR) != 0) { in rootread()
72 return dirread(channel, dir, NULL, 0, rootgen); in rootread()
76 assert(channel->qid != DEV_ROOT_QBLOBCTL); in rootread()
78 dp = &blobtab[channel->qid - DEV_ROOT_QBLOBCTL]; in rootread()
[all …]
/arm-trusted-firmware-2.8.0/drivers/arm/mhu/
A Dmhu_v2_x.h96 uint32_t channel, uint32_t val);
113 uint32_t channel, uint32_t *value);
129 uint32_t channel);
146 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value);
163 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
180 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
A Dmhu_v2_x.c209 uint32_t channel, uint32_t val) in mhu_v2_x_channel_send() argument
222 (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; in mhu_v2_x_channel_send()
230 uint32_t channel, uint32_t *value) in mhu_v2_x_channel_poll() argument
243 *value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st; in mhu_v2_x_channel_poll()
251 uint32_t channel) in mhu_v2_x_channel_clear() argument
264 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; in mhu_v2_x_channel_clear()
285 *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; in mhu_v2_x_channel_receive()
293 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set() argument
306 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; in mhu_v2_x_channel_mask_set()
314 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_clear() argument
[all …]
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/
A Dsuspend.c128 channel &= 0x1; in rkclk_ddr_reset()
133 CRU_SFTRST_DDR_PHY(channel, phy)); in rkclk_ddr_reset()
787 uint32_t channel; in dmc_resume() local
811 for (channel = 0; channel < sdram_params->num_channels; channel++) { in dmc_resume()
812 phy_pctrl_reset(channel); in dmc_resume()
820 pctl_cfg(channel, sdram_params); in dmc_resume()
823 for (channel = 0; channel < 2; channel++) { in dmc_resume()
824 if (sdram_params->ch[channel].col) in dmc_resume()
825 channel_mask |= 1 << channel; in dmc_resume()
831 for (channel = 0; channel < sdram_params->num_channels; channel++) { in dmc_resume()
[all …]
A Ddfs.c82 uint8_t channel, uint8_t cs) in get_cs_die_capability() argument
84 struct rk3399_sdram_channel *ch = &ram_config->ch[channel]; in get_cs_die_capability()
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/
A Dhikey960_boardid.c63 static int get_adc(unsigned int channel, unsigned int *value) in get_adc() argument
67 if (channel > HKADC_CHANNEL_MAX) { in get_adc()
68 WARN("invalid channel:%d\n", channel); in get_adc()
72 mmio_write_32(HKADC_WR01_DATA_REG, HKADC_WR01_VALUE | channel); in get_adc()
97 static int get_value(unsigned int channel, unsigned int *value) in get_value() argument
101 ret = get_adc(channel, value); in get_value()
/arm-trusted-firmware-2.8.0/plat/socionext/synquacer/drivers/scp/
A Dsq_scmi.c94 static scmi_channel_t channel; variable
226 channel.info = &sq_scmi_plat_info; in plat_sq_pwrc_setup()
227 channel.lock = SQ_SCMI_LOCK_GET_INSTANCE; in plat_sq_pwrc_setup()
228 sq_scmi_handle = scmi_init(&channel); in plat_sq_pwrc_setup()
233 if (scmi_ap_core_init(&channel) < 0) { in plat_sq_pwrc_setup()
/arm-trusted-firmware-2.8.0/drivers/marvell/secure_dfx_access/
A Darmada_thermal.c166 static void armada_select_channel(int channel) in armada_select_channel() argument
179 if (channel) { in armada_select_channel()
185 ctrl0 |= (channel - 1) << TSEN_CTRL0_CHAN_SHIFT; in armada_select_channel()
/arm-trusted-firmware-2.8.0/docs/perf/
A Dpsci-performance-juno.rst139 communication channel. This is compounded by the SCP firmware waiting for each
140 AP CPU to enter WFI before making the channel available to other CPUs, which
/arm-trusted-firmware-2.8.0/docs/threat_model/
A Dthreat_model.rst483 | | side-channel information that can be used by an |
738 | | | Microarchitectural side-channel attacks such as |
763 | Mitigations | Enable appropriate side-channel protections. |
835 | | mount side-channel attacks using information |
843 | | side-channel timing attacks against TF-A. |
A Dthreat_model_spm.rst533 | | side-channel attack techniques.** |
559 | | side-channel type of attacks. |
620 | | creating the possibility for a channel that was not|
696 | | malicious, communication channel is established. |
A Dthreat_model_el3_spm.rst494 | | side-channel attack techniques.** |
/arm-trusted-firmware-2.8.0/docs/process/
A Dsecurity-hardening.rst72 would allow it to carry out side-channel timing attacks against the Secure
/arm-trusted-firmware-2.8.0/docs/
A Dchange-log.md2760 …- generate two memory nodes for larger than 2 GiB channel 0 ([21924f2](https://review.trustedfirmw…
3338 - Select MMC_CH1 for eMMC channel
3634 - Checked channel index before calling clone function
4415 - arm/sgi: Fix the incorrect check for SCMI channel ID

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