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/arm-trusted-firmware-2.8.0/fdts/
A Drtsm_ve-motherboard.dtsi14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24000000>;
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
47 /* CLCD clock */
51 #clock-cells = <0>;
[all …]
A Dfvp-foundation-motherboard.dtsi21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <24000000>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <1000000>;
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <32768>;
59 #clock-cells = <1>;
[all …]
A Dcorstone700.dtsi51 compatible = "fixed-clock";
52 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <48000000>;
66 /* UART clock - 32MHz */
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
118 clock-names = "apb_pclk";
130 clock-names = "apb_pclk";
[all …]
A Da5ds.dts68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <7500000>;
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <24000000>;
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
94 clock-names = "apb_pclk";
113 clock-names = "apb_pclk";
[all …]
A Dn1sdp-single-chip.dts34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <60000000>;
37 clock-output-names = "iofpga_clk";
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <23750000>;
44 clock-output-names = "hdlcdclk";
52 clock-names = "pxlclk";
66 clock-frequency = <400000>;
A Dfvp-ve-Cortex-A5x1.dts56 clock-names = "pxlclk";
85 #clock-cells = <0>;
86 clock-output-names = "oscclk0";
94 #clock-cells = <0>;
95 clock-output-names = "oscclk1";
103 #clock-cells = <0>;
104 clock-output-names = "oscclk2";
112 #clock-cells = <0>;
121 #clock-cells = <0>;
126 /* SMB clock */
[all …]
A Dmorello.dtsi62 clock-names = "apb_pclk";
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <50000000>;
88 clock-output-names = "apb_pclk";
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <50000000>;
95 clock-output-names = "uartclk";
103 clock-names = "uartclk", "apb_pclk";
A Dtc.dts280 #clock-cells = <1>;
285 #clock-cells = <1>;
311 #clock-cells = <0>;
318 #clock-cells = <0>;
325 #clock-cells = <0>;
378 clock-names = "pxlclk";
390 #clock-cells = <0>;
419 #clock-cells = <0>;
487 clock-names = "aclk";
494 clock-names = "pxclk";
[all …]
A Darm_fpga.dts68 compatible = "fixed-clock";
69 #clock-cells = <0>;
70 clock-frequency = <100000000>;
71 clock-output-names = "apb_pclk";
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <10000000>;
78 clock-output-names = "uartclk";
86 clock-names = "uartclk", "apb_pclk";
A Dstm32mp131.dtsi23 clock-names = "cpu";
31 #clock-cells = <0>;
32 compatible = "fixed-clock";
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
51 clock-frequency = <32768>;
55 #clock-cells = <0>;
139 clock-names = "otg";
219 #clock-cells = <1>;
[all …]
A Dstm32mp151.dtsi42 #clock-cells = <0>;
48 #clock-cells = <0>;
54 #clock-cells = <0>;
56 clock-frequency = <32768>;
60 #clock-cells = <0>;
66 #clock-cells = <0>;
85 clock-names = "int";
174 clock-names = "int";
182 clock-names = "otg";
199 #clock-cells = <1>;
[all …]
A Dmorello-fvp.dts128 clock-names = "KMIREFCLK", "apb_pclk";
136 clock-names = "KMIREFCLK", "apb_pclk";
150 #clock-cells = <1>;
156 compatible = "fixed-clock";
157 #clock-cells = <0>;
158 clock-frequency = <24000000>;
159 clock-output-names = "bp:clock24mhz";
A Dfvp-ve-Cortex-A7x1.dts63 /* Reference 24MHz clock x 2 */
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <48000000>;
67 clock-output-names = "smclk";
A Dn1sdp.dtsi71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <100000000>;
74 clock-output-names = "apb_pclk";
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <50000000>;
81 clock-output-names = "uartclk";
206 clock-names = "uartclk", "apb_pclk";
A Dmorello-soc.dts164 clock-names = "aclk";
171 clock-names = "pxclk";
191 clock-frequency = <100000>;
209 /* 77.1 MHz derived from 24 MHz reference clock */
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <350000000>;
213 clock-output-names = "aclk";
226 #clock-cells = <1>;
230 #clock-cells = <1>;
/arm-trusted-firmware-2.8.0/plat/st/stm32mp1/
A Dstm32mp1_scmi.c139 .clock = stm32_scmi0_clock,
254 if ((clock == NULL) || in plat_scmi_clock_get_name()
259 return clock->name; in plat_scmi_clock_get_name()
267 if (clock == NULL) { in plat_scmi_clock_rates_array()
291 if ((clock == NULL) || in plat_scmi_clock_get_rate()
303 if ((clock == NULL) || in plat_scmi_clock_get_state()
316 if (clock == NULL) { in plat_scmi_clock_set_state()
325 if (!clock->enabled) { in plat_scmi_clock_set_state()
328 clock->enabled = true; in plat_scmi_clock_set_state()
331 if (clock->enabled) { in plat_scmi_clock_set_state()
[all …]
/arm-trusted-firmware-2.8.0/drivers/st/crypto/
A Dstm32_hash.c86 unsigned int clock; member
223 clk_enable(stm32_hash.clock); in stm32_hash_update()
265 clk_disable(stm32_hash.clock); in stm32_hash_update()
274 clk_enable(stm32_hash.clock); in stm32_hash_final()
294 clk_disable(stm32_hash.clock); in stm32_hash_final()
314 clk_enable(stm32_hash.clock); in stm32_hash_init()
318 clk_disable(stm32_hash.clock); in stm32_hash_init()
340 if (hash_info.clock < 0) { in stm32_hash_register()
345 stm32_hash.clock = hash_info.clock; in stm32_hash_register()
347 clk_enable(stm32_hash.clock); in stm32_hash_register()
[all …]
A Dstm32_rng.c58 unsigned long clock; member
91 clock_rate = clk_get_rate(stm32_rng.clock); in stm32_rng_clock_freq_restrain()
102 VERBOSE("RNG clk rate : %lu\n", clk_get_rate(stm32_rng.clock) >> clock_div); in stm32_rng_clock_freq_restrain()
243 if (dt_rng.clock < 0) { in stm32_rng_init()
247 stm32_rng.clock = (unsigned long)dt_rng.clock; in stm32_rng_init()
248 clk_enable(stm32_rng.clock); in stm32_rng_init()
/arm-trusted-firmware-2.8.0/drivers/st/iwdg/
A Dstm32_iwdg.c34 unsigned long clock; member
65 clk_enable(iwdg->clock); in stm32_iwdg_refresh()
70 clk_disable(iwdg->clock); in stm32_iwdg_refresh()
98 iwdg->clock = (unsigned long)dt_info.clock; in stm32_iwdg_init()
/arm-trusted-firmware-2.8.0/drivers/st/clk/
A Dstm32mp1_clk.c852 unsigned long clock = 0; in get_clock_rate() local
861 clock = stm32mp1_clk_get_fixed(_HSI); in get_clock_rate()
874 clock >>= stm32mp1_mpu_div[clkdiv]; in get_clock_rate()
981 clock = stm32mp1_clk_get_fixed(_HSI); in get_clock_rate()
985 clock = stm32mp1_clk_get_fixed(_CSI); in get_clock_rate()
989 clock = stm32mp1_clk_get_fixed(_HSE); in get_clock_rate()
995 clock = stm32mp1_clk_get_fixed(_HSE); in get_clock_rate()
999 clock = stm32mp1_clk_get_fixed(_LSI); in get_clock_rate()
1002 clock = stm32mp1_clk_get_fixed(_LSE); in get_clock_rate()
1043 clock = USB_PHY_48_MHZ; in get_clock_rate()
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/include/drivers/
A Dspe.h20 int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
/arm-trusted-firmware-2.8.0/drivers/st/gpio/
A Dstm32_gpio.c230 unsigned long clock = stm32_get_gpio_bank_clock(bank); in set_gpio() local
234 clk_enable(clock); in set_gpio()
283 clk_disable(clock); in set_gpio()
302 unsigned long clock = stm32_get_gpio_bank_clock(bank); in set_gpio_secure_cfg() local
306 clk_enable(clock); in set_gpio_secure_cfg()
314 clk_disable(clock); in set_gpio_secure_cfg()
/arm-trusted-firmware-2.8.0/plat/imx/common/include/
A Dimx_uart.h14 int console_imx_uart_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
/arm-trusted-firmware-2.8.0/include/drivers/renesas/rcar/console/
A Dconsole.h20 int console_rcar_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
/arm-trusted-firmware-2.8.0/include/drivers/amlogic/
A Dmeson_console.h25 int console_meson_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,

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