| /arm-trusted-firmware-2.8.0/plat/xilinx/zynqmp/pm_service/ |
| A D | pm_api_clock.h | 59 enum clock_id { enum
293 struct pm_pll *pm_clock_get_pll(enum clock_id clock_id);
294 struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id);
297 void pm_api_clock_get_name(uint32_t clock_id, char *name);
310 enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id,
314 enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id,
316 enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id);
323 enum clock_id clock_id,
326 enum clock_id clock_id,
328 enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id,
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| A D | pm_api_sys.c | 980 pm_api_clock_get_name(clock_id, name); in pm_clock_get_name()
1078 status = pm_clock_id_is_valid(clock_id); in pm_clock_gate()
1116 pll = pm_clock_get_pll(clock_id); in pm_clock_enable()
1122 return pm_clock_gate(clock_id, 1); in pm_clock_enable()
1140 pll = pm_clock_get_pll(clock_id); in pm_clock_disable()
1146 return pm_clock_gate(clock_id, 0); in pm_clock_disable()
1167 pll = pm_clock_get_pll(clock_id); in pm_clock_getstate()
1172 status = pm_clock_id_is_valid(clock_id); in pm_clock_getstate()
1210 status = pm_clock_id_is_valid(clock_id); in pm_clock_setdivider()
1255 status = pm_clock_id_is_valid(clock_id); in pm_clock_getdivider()
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| A D | pm_api_clock.c | 2449 if (clock_id == CLK_MAX) { in pm_api_clock_get_name()
2659 enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, in pm_api_clock_get_max_divisor() argument
2699 const enum clock_id cid;
2702 const enum clock_id div2;
2752 struct pm_pll *pm_clock_get_pll(enum clock_id clock_id) in pm_clock_get_pll() argument
2772 enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id, in pm_clock_get_pll_node_id() argument
2791 struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id) in pm_clock_get_pll_by_related_clk() argument
2896 enum clock_id clock_id, in pm_clock_pll_set_parent() argument
2929 enum clock_id clock_id, in pm_clock_pll_get_parent() argument
2964 enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, in pm_clock_set_pll_mode() argument
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| A D | pm_api_sys.h | 136 enum pm_ret_status pm_clock_enable(uint32_t clock_id);
137 enum pm_ret_status pm_clock_disable(uint32_t clock_id);
138 enum pm_ret_status pm_clock_getstate(uint32_t clock_id,
140 enum pm_ret_status pm_clock_setdivider(uint32_t clock_id,
142 enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
144 enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
146 enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
148 enum pm_ret_status pm_clock_setparent(uint32_t clock_id,
150 enum pm_ret_status pm_clock_getparent(uint32_t clock_id,
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| /arm-trusted-firmware-2.8.0/drivers/scmi-msg/ |
| A D | clock.c | 138 unsigned int clock_id = 0U; in scmi_clock_attributes() local
145 clock_id = SPECULATION_SAFE_VALUE(in_args->clock_id); in scmi_clock_attributes()
162 clock_id); in scmi_clock_attributes()
174 unsigned int clock_id = 0U; in scmi_clock_rate_get() local
181 clock_id = SPECULATION_SAFE_VALUE(in_args->clock_id); in scmi_clock_rate_get()
201 unsigned int clock_id = 0U; in scmi_clock_rate_set() local
208 clock_id = SPECULATION_SAFE_VALUE(in_args->clock_id); in scmi_clock_rate_set()
228 unsigned int clock_id = 0U; in scmi_clock_config_set() local
235 clock_id = SPECULATION_SAFE_VALUE(in_args->clock_id); in scmi_clock_config_set()
285 unsigned int clock_id; in scmi_clock_describe_rates() local
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| A D | clock.h | 36 uint32_t clock_id; member
52 uint32_t clock_id; member
84 uint32_t clock_id; member
102 uint32_t clock_id; member
140 uint32_t clock_id; member
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| /arm-trusted-firmware-2.8.0/plat/st/stm32mp1/ |
| A D | stm32mp1_scmi.c | 31 unsigned long clock_id; member
75 .clock_id = _id, \
255 !stm32mp_nsec_can_access_clock(clock->clock_id)) { in plat_scmi_clock_get_name()
271 if (!stm32mp_nsec_can_access_clock(clock->clock_id)) { in plat_scmi_clock_rates_array()
278 *array = clk_get_rate(clock->clock_id); in plat_scmi_clock_rates_array()
292 !stm32mp_nsec_can_access_clock(clock->clock_id)) { in plat_scmi_clock_get_rate()
296 return clk_get_rate(clock->clock_id); in plat_scmi_clock_get_rate()
327 clk_enable(clock->clock_id); in plat_scmi_clock_set_state()
333 clk_disable(clock->clock_id); in plat_scmi_clock_set_state()
464 stm32mp_nsec_can_access_clock(clk->clock_id)) { in stm32mp1_init_scmi_server()
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| A D | stm32mp1_shared_resources.c | 376 bool stm32mp_nsec_can_access_clock(unsigned long clock_id) in stm32mp_nsec_can_access_clock() argument
380 switch (clock_id) { in stm32mp_nsec_can_access_clock()
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| /arm-trusted-firmware-2.8.0/include/drivers/st/ |
| A D | stm32_sdmmc2.h | 24 unsigned int clock_id; member
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| A D | stm32_pka.h | 34 unsigned long clock_id; member
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| A D | stm32_saes.h | 18 unsigned long clock_id; member
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| /arm-trusted-firmware-2.8.0/plat/st/common/include/ |
| A D | stm32mp_shared_resources.h | 17 bool stm32mp_nsec_can_access_clock(unsigned long clock_id);
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| /arm-trusted-firmware-2.8.0/drivers/st/spi/ |
| A D | stm32_qspi.c | 112 unsigned long clock_id; member
363 unsigned long qspi_clk = clk_get_rate(stm32_qspi.clock_id); in stm32_qspi_set_speed()
490 stm32_qspi.clock_id = (unsigned long)info.clock; in stm32_qspi_init()
493 clk_enable(stm32_qspi.clock_id); in stm32_qspi_init()
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| /arm-trusted-firmware-2.8.0/drivers/st/mmc/ |
| A D | stm32_sdmmc2.c | 712 sdmmc2_params.clock_id = dt_info.clock; in stm32_sdmmc2_dt_get_config()
775 clk_enable(sdmmc2_params.clock_id); in stm32_sdmmc2_mmc_init()
792 sdmmc2_params.clk_rate = clk_get_rate(sdmmc2_params.clock_id); in stm32_sdmmc2_mmc_init()
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| /arm-trusted-firmware-2.8.0/drivers/st/fmc/ |
| A D | stm32_fmc2_nand.c | 150 unsigned long clock_id; member
165 unsigned long hclk = clk_get_rate(stm32_fmc2.clock_id); in stm32_fmc2_nand_setup_timing()
821 stm32_fmc2.clock_id = (unsigned long)info.clock; in stm32_fmc2_init()
912 clk_enable(stm32_fmc2.clock_id); in stm32_fmc2_init()
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| /arm-trusted-firmware-2.8.0/drivers/st/crypto/ |
| A D | stm32_pka.c | 289 pka_pdata.clock_id = (unsigned long)info.clock; in stm32_pka_parse_fdt()
592 clk_enable(pka_pdata.clock_id); in stm32_pka_init()
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| A D | stm32_saes.c | 176 pdata->clock_id = (unsigned long)info.clock; in stm32_saes_parse_fdt()
398 clk_enable(saes_pdata.clock_id); in stm32_saes_driver_init()
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| /arm-trusted-firmware-2.8.0/drivers/st/clk/ |
| A D | stm32mp1_clk.c | 2296 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) in stm32mp1_register_clock_parents_secure() argument
2304 switch (clock_id) { in stm32mp1_register_clock_parents_secure()
2318 parent_id = stm32mp1_clk_get_parent(clock_id); in stm32mp1_register_clock_parents_secure()
2320 INFO("No parent found for clock %lu\n", clock_id); in stm32mp1_register_clock_parents_secure()
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