Searched refs:cluster_addr (Results 1 – 4 of 4) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8183/drivers/spmc/ |
| A D | mtspmc_private.h | 14 int cluster_addr; member
18 #define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
20 #define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
107 [0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
108 [1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
113 [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
114 [1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
196 [0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
197 [1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
229 [0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
[all …]
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8192/drivers/spmc/ |
| A D | mtspmc_private.h | 23 unsigned int cluster_addr; member
28 (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
30 #define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
90 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
116 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
121 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
173 { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
177 { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
181 { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/spmc/ |
| A D | mtspmc_private.h | 23 unsigned int cluster_addr; member
28 (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
30 #define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
90 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
116 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
121 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
172 { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
176 { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
180 { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8186/drivers/spmc/ |
| A D | mtspmc_private.h | 21 unsigned int cluster_addr; member
26 (reg[cluster].cluster_addr + (cpu << reg[cluster].cpu_stride))
28 #define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
88 { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2U }
93 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
110 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG8, .cpu_stride = 3U }
115 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
165 { .cluster_addr = PTP3_CPU0_SPMC_SW_CFG, .cpu_stride = 11U }
169 { .cluster_addr = CPU0_ILDO_CONTROL5, .cpu_stride = 11U }
173 { .cluster_addr = CPU0_ILDO_CONTROL8, .cpu_stride = 11U }
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