| /arm-trusted-firmware-2.8.0/lib/extensions/sve/ |
| A D | sve.c | 33 void sve_enable(cpu_context_t *context) in sve_enable() argument
41 cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); in sve_enable()
45 write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); in sve_enable()
48 write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, in sve_enable()
52 void sve_disable(cpu_context_t *context) in sve_disable() argument
63 state = get_el3state_ctx(context); in sve_disable()
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| /arm-trusted-firmware-2.8.0/lib/extensions/sme/ |
| A D | sme.c | 32 void sme_enable(cpu_context_t *context) in sme_enable() argument
41 sve_enable(context); in sme_enable()
46 state = get_el3state_ctx(context); in sme_enable()
80 sve_enable(context); in sme_enable()
83 void sme_disable(cpu_context_t *context) in sme_disable() argument
91 sve_disable(context); in sme_disable()
96 state = get_el3state_ctx(context); in sme_disable()
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| /arm-trusted-firmware-2.8.0/bl31/ |
| A D | bl31_context_mgmt.c | 31 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
36 context); in cm_set_context()
58 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
65 context); in cm_set_context_by_index()
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| /arm-trusted-firmware-2.8.0/include/lib/el3_runtime/ |
| A D | context_mgmt.h | 28 void *context,
31 void cm_set_context(void *context, uint32_t security_state);
63 static inline void cm_set_next_context(void *context) in cm_set_next_context() argument
81 : : "r" (context)); in cm_set_next_context()
86 void cm_set_next_context(void *context);
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| /arm-trusted-firmware-2.8.0/include/lib/extensions/ |
| A D | sve.h | 12 void sve_enable(cpu_context_t *context);
13 void sve_disable(cpu_context_t *context);
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| A D | sme.h | 24 void sme_enable(cpu_context_t *context);
25 void sme_disable(cpu_context_t *context);
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| A D | sys_reg_trace.h | 13 void sys_reg_trace_enable(cpu_context_t *context);
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | context_mgmt_rework.rst | 13 The context management library in TF-A provides the basic CPU context
33 (1) **Decentralized model for context mgmt**
45 initialize the Non Secure world context.
59 (3) **Maintain EL3 sysregs which affect lower EL within CPU context**
62 basis (eg: cptr_el3, scr_el3, zcr_el3 is part of the context
106 context. The proposal here is to move the conditional initialization
140 to S-EL2 as SPM can take care of saving the incoming NS EL1 context.
165 The proposal here is to maintain a separate root world CPU context
169 sequence for this Root context would need to be done in
172 of Root world context would need to be saved on EL3 exit (eg: SP_EL0).
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| /arm-trusted-firmware-2.8.0/drivers/nxp/crypto/caam/src/auth/ |
| A D | hash.c | 64 int hash_update(enum hash_algo algo, void *context, void *data_ptr, in hash_update() argument
67 struct hash_ctx *ctx = context; in hash_update()
111 int hash_final(enum hash_algo algo, void *context, void *hash_ptr, in hash_final() argument
115 struct hash_ctx *ctx = context; in hash_final()
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| /arm-trusted-firmware-2.8.0/bl32/sp_min/ |
| A D | sp_min_main.c | 79 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
82 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; in cm_set_context()
102 void cm_set_context_by_index(unsigned int cpu_idx, void *context, in cm_set_context_by_index() argument
106 sp_min_cpu_ctx_ptr[cpu_idx] = context; in cm_set_context_by_index()
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/crypto/caam/ |
| A D | hash.h | 80 int hash_update(enum hash_algo algo, void *context, void *data_ptr,
82 int hash_final(enum hash_algo algo, void *context, void *hash_ptr,
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-8.rst | 26 When taking an exception to EL3, BL31 saves the CPU context. The aim is to
29 ``x0`` to ``x3`` are not part of the CPU context saved on the stack.
33 into the CPU context, typically using one of the ``SMC_RETx()`` macros provided
38 CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
39 can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
46 * CPU context. x30 register must be explicitly restored by the caller.
53 remaining ones are left unchanged in the CPU context. As a result,
67 For this reason, TF-A does not save ``x0`` to ``x3`` in the CPU context on an
90 * spsr, lr, sp registers and the `scr` register to the SMC context on entry
97 /* Save r0 - r12 in the SMC context */
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| A D | security-advisory-tfv-5.rst | 45 sensible default values in the secure context.
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| /arm-trusted-firmware-2.8.0/bl1/aarch32/ |
| A D | bl1_context_mgmt.c | 56 void cm_set_next_context(void *context) in cm_set_next_context() argument
58 assert(context != NULL); in cm_set_next_context()
59 bl1_next_cpu_context_ptr = context; in cm_set_next_context()
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| /arm-trusted-firmware-2.8.0/bl1/aarch64/ |
| A D | bl1_context_mgmt.c | 28 void cm_set_context(void *context, uint32_t security_state) in cm_set_context() argument
31 bl1_cpu_context_ptr[security_state] = context; in cm_set_context()
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | psci-lib-integration-guide.rst | 37 context.
44 to programming. See `PSCI CPU context management`_ for more
45 details on CPU context management.
56 initializes/restores the non-secure CPU context as well.
63 #. On receipt of an SMC, save the register context as per `SMCCC`_.
73 PSCI CPU context management
84 The EL3 Runtime Software is responsible for managing register context
117 to CPU context ``cpu_context_t`` data and these are described in
288 - Restores/Initializes the non-secure context and populates the
345 APIs to store and retrieve pointers to this CPU context data. SP-MIN
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| /arm-trusted-firmware-2.8.0/bl1/ |
| A D | bl1.mk | 25 lib/el3_runtime/aarch64/context.S
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | xlat-tables-lib-v2-design.rst | 137 the default translation context or on an alternative one.
146 ``foo``, the context variable name will be ``foo_xlat_ctx``.
154 Number of translation tables to statically allocate for this context,
158 for this context.
162 Size in bytes of the virtual address space to map using this context. This
169 Size in bytes of the physical address space to map using this context.
171 The default translation context is internally initialized using information
302 the translation tables context affected by them.
306 - **Active context module**
327 translation context to work on.
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| A D | secure-partition-manager.rst | 154 restoring) the EL2 system register context before entering (resp.
156 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
551 - Pinned MP SPs: an execution context matches a physical PE. MP SPs must
556 the single execution context.
738 a specific execution context, as determined by the sender.
972 from its first execution context, to provide the entry point address for
1060 configuration is made part of a vCPU context.
1086 - RTM_FFA_RUN: runtime model presented to an execution context that is
1150 execution context.
1214 completion by target SP execution context.
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| A D | rmm-el3-comms-spec.rst | 487 As part of NS world switch, EL3 is expected to maintain a register context
492 EL3 must maintain a separate register context for the following:
495 …#. EL2 system register context for all enabled features by EL3. These include system registers wit…
501 EL3 will always copy x0-x4 from Realm context to NS Context.
515 SMCCC v1.3 allows NS world to specify whether SVE context is in use. In this
516 case, RMM could choose to not save the incoming SVE context but must ensure
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| A D | realm-management-extension.rst | 36 Changes to context management
38 A new CPU context for the Realm world has been added. The existing
39 :ref:`CPU context management API<PSCI Library Integration guide for Armv8-A
40 AArch32 systems>` can be used to manage Realm context.
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| /arm-trusted-firmware-2.8.0/lib/psci/ |
| A D | psci_lib.mk | 24 PSCI_LIB_SOURCES += lib/el3_runtime/aarch64/context.S
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| /arm-trusted-firmware-2.8.0/tools/conventional-changelog-tf-a/ |
| A D | index.js | 168 writerOpts.transform = function (commit, context) { argument
182 return ccWriterOptsTransform(commit, context);
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | interrupt-framework-design.rst | 37 context. It is always handled in Secure-EL1.
41 current execution context. It is always handled in either Non-secure EL1
45 depending upon the security state of the current execution context. It is
195 For example, in Arm GICv3, when the execution context is Secure-EL1/
341 via the context management library APIs.
712 the interrupt, a context switch is required. The following 2 cases
713 require a context switch from secure to non-secure or vice-versa:
784 #. It ensures that the secure CPU context is used to program the next
874 restoring non secure context.
889 #. Restores the secure context by calling
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| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model_spm.rst | 238 | ``Mitigations`` | In context of FF-A v1.0 this is the case of sharing|
882 | | execution context. |
894 | | execution context using FFA_MSG_SEND_DIRECT_REQ |
990 | | execution context by the SPMC even before secure |
1014 | | context responsible for handling the various |
1019 | | signaled to an execution context of a secure |
1026 | | current execution context. |
1144 | | execution context in SPMC schedule mode which |
1150 | | execution context to make progress even upon being |
|