| /arm-trusted-firmware-2.8.0/drivers/mentor/i2c/ |
| A D | mi2cv.c | 73 reg = mmio_read_32((uintptr_t)&base->control); in mentor_i2c_interrupt_clear()
79 mmio_write_32((uintptr_t)&base->control, reg); in mentor_i2c_interrupt_clear()
89 reg = mmio_read_32((uintptr_t)&base->control); in mentor_i2c_interrupt_get()
115 mmio_write_32((uintptr_t)&base->control, in mentor_i2c_start_bit_set()
116 mmio_read_32((uintptr_t)&base->control) | in mentor_i2c_start_bit_set()
131 if ((mmio_read_32((uintptr_t)&base->control) & in mentor_i2c_start_bit_set()
158 mmio_write_32((uintptr_t)&base->control, in mentor_i2c_stop_bit_set()
159 mmio_read_32((uintptr_t)&base->control) | in mentor_i2c_stop_bit_set()
459 mmio_write_32((uintptr_t)&base->control, in i2c_init()
467 mmio_write_32((uintptr_t)&base->control, in i2c_init()
[all …]
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| /arm-trusted-firmware-2.8.0/docs/resources/diagrams/plantuml/ |
| A D | fip-secure-partitions.puml | 60 control sp_mk_generator
71 control dtc
72 control sptool
124 control crttool
125 control fiptool
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| /arm-trusted-firmware-2.8.0/plat/allwinner/common/include/ |
| A D | mentor_i2c_plat.h | 22 uint32_t control; member
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| /arm-trusted-firmware-2.8.0/plat/marvell/armada/a8k/common/include/ |
| A D | mentor_i2c_plat.h | 21 uint32_t control; member
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | allwinner.rst | 46 - ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown
48 to be loaded into the ARISC SCP (A64, H5), or the power sequence control
50 control, like core on/off and system off/reset.
52 is detected at runtime, this control scheme will be ignored, and SCPI
55 - ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and
66 software like U-Boot to ignore power control via the PMIC.
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| A D | imx8.rst | 19 control for system-level resources on i.MX8. The heart of the system
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| A D | socionext-uniphier.rst | 15 expands BL2 there, and hands the control over to it. Therefore, all images
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| /arm-trusted-firmware-2.8.0/tools/marvell/doimage/secure/ |
| A D | sec_img_7K.cfg | 29 control = [0xF2441920, 0xF2441940];
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| A D | sec_img_8K.cfg | 29 control = [0xF2441920, 0xF2441940, 0xF4441920, 0xF4441940];
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp157a-avenger96.dts | 53 st,main-control-register = <0x04>;
54 st,vin-control-register = <0xc0>;
55 st,usb-control-register = <0x30>;
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| /arm-trusted-firmware-2.8.0/drivers/brcm/emmc/ |
| A D | emmc_chal_sd.c | 833 uint32_t control, flag; in chal_sd_reset_line() local
846 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_reset_line()
848 control |= line; in chal_sd_reset_line()
850 control); in chal_sd_reset_line()
854 control = mmio_read_32(handle->ctrl.sdRegBaseAddr + in chal_sd_reset_line()
856 } while (control & line); in chal_sd_reset_line()
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| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | alt-boot-flows.rst | 18 other BL images and passing control to BL31. It reduces the complexity of
57 moment for a debugger to take control of the target and load the payload (for
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| A D | interrupt-framework-design.rst | 10 (normal world). The framework should then take care of handing control of
13 that secure interrupts are under the control of the secure software with
100 control of handling secure interrupts.
122 software is in control of how its execution is preempted by non-secure
148 in Secure-EL1/Secure-EL0 is in control of how its execution is preempted
223 #. Implementing support to hand control of an interrupt type to its
446 #. It passes control to the Test Secure Payload to perform its
733 priorities before handing control to the SP.
933 The TSPD hands control of a Secure-EL1 interrupt to the TSP at the
944 ``tsp_handle_preemption()`` to handover control back to EL3 by issuing
[all …]
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| A D | firmware-design.rst | 9 to the stage where it hands-off control to firmware running in the normal
366 #. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
372 BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
443 relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
469 #. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
477 #. BL1 passes control to BL31 at the specified entrypoint at EL3.
539 The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
561 `SMC Calling Convention`_ before passing control to the required SMC
1135 In the absence of a BL32 image, BL31 passes control to the normal world
1149 TF-A supports two approaches for the SPD to pass control to BL32 before
[all …]
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | drtm_poc.rst | 34 signature, and transfers control to it.
39 and finally transfers control to the payload.
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | image-terminology.rst | 58 location, then hand-off control to that image.
66 executable RAM locations, then hand-off control to the EL3 Runtime Firmware.
118 location, then hand-off control to that image. This may be performed in
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-2.rst | 41 A similar issue applies to the ``MDCR_EL3.SPD32`` bits, which control AArch32
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| A D | security-advisory-tfv-3.rst | 29 contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
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| A D | security-advisory-tfv-9.rst | 47 code is under attacker control.
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| A D | security-advisory-tfv-7.rst | 41 control bit to prevent the re-ordering of stores and loads.
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| A D | security-advisory-tfv-4.rst | 104 Similarly, if an attacker has control over the ``image_src`` or ``image_size``
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | glossary.rst | 30 control flow integrity around indirect branches and their targets.
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| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | secure-partition-manager-mm.rst | 55 under the control of privileged software, provides one or more services and
104 the control of the SPM. Hence common programming concepts described below are
122 preempted to give control back to the Normal world).
247 - Interfaces that establish the control path between the SPM and the Secure
268 SMC request, Trusted Firmware-A returns control directly to S-EL0 through an
593 syndrome information can be used to return control through an ERET
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| A D | firmware-update.rst | 219 passed execution control to it.
284 This SMC passes execution control to an EL3 image described by the provided
286 this SMC for BL1 to pass execution control to BL31.
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| /arm-trusted-firmware-2.8.0/docs/about/ |
| A D | features.rst | 14 - Initialization of the secure world, for example exception vectors, control
|