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/arm-trusted-firmware-2.8.0/fdts/
A Dfvp-base-gicv3.dtsi10 gic: interrupt-controller@2f000000 {
16 interrupt-controller;
24 its: msi-controller@2f020000 {
26 msi-controller;
A Dstm32mp151.dtsi35 interrupt-controller;
251 * controller.
546 gpio-controller;
557 gpio-controller;
568 gpio-controller;
579 gpio-controller;
590 gpio-controller;
601 gpio-controller;
612 gpio-controller;
623 gpio-controller;
[all …]
A Dstm32mp131.dtsi64 interrupt-controller;
251 interrupt-controller;
476 gpio-controller;
488 gpio-controller;
500 gpio-controller;
512 gpio-controller;
524 gpio-controller;
536 gpio-controller;
548 gpio-controller;
560 gpio-controller;
[all …]
A Dfvp-base-gicv2.dtsi10 gic: interrupt-controller@2f000000 {
14 interrupt-controller;
A Darm_fpga.dts11 #include <dt-bindings/interrupt-controller/arm-gic.h>
89 gic: interrupt-controller@30000000 {
95 interrupt-controller;
101 its: msi-controller@30040000 {
105 msi-controller;
A Dmorello-soc.dts241 its1: msi-controller@30040000 {
243 msi-controller;
248 its2: msi-controller@30060000 {
250 msi-controller;
255 its_ccix: msi-controller@30080000 {
257 msi-controller;
262 its_pcie: msi-controller@300a0000 {
264 msi-controller;
A Dn1sdp.dtsi6 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 gic: interrupt-controller@30000000 {
96 interrupt-controller;
104 msi-controller;
111 msi-controller;
118 msi-controller;
125 msi-controller;
A Dfvp-foundation-gicv3-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 gic: interrupt-controller@2f000000 {
96 interrupt-controller;
106 msi-controller;
A Dfvp-ve-Cortex-A7x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
50 gic: interrupt-controller@2c001000 {
54 interrupt-controller;
A Dmorello.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 gic: interrupt-controller@2c010000 {
26 interrupt-controller;
A Dfvp-foundation-gicv2-psci.dts14 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 gic: interrupt-controller@2f000000 {
94 interrupt-controller;
A Da5ds.dts57 L2: cache-controller@1C010000 {
97 gic: interrupt-controller@1c001000 {
101 interrupt-controller;
A Dcorstone700.dtsi7 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 gic: interrupt-controller@1c000000 {
38 interrupt-controller;
A Dfvp-ve-Cortex-A5x1.dts7 #include <dt-bindings/interrupt-controller/arm-gic.h>
70 gic: interrupt-controller@2c001000 {
74 interrupt-controller;
A Dn1sdp-multi-chip.dts103 msi-controller;
110 msi-controller;
A Dstm32mp15-bl32.dtsi21 /delete-node/ memory-controller@58002000;
A Dstm32mp157c-ev1.dts28 nand-controller@4,0 {
A Dstm32mp13-bl2.dtsi19 /delete-node/ memory-controller@58002000;
/arm-trusted-firmware-2.8.0/plat/renesas/common/
A Drcar_common.c25 static int rcar_pcie_fixup(unsigned int controller) in rcar_pcie_fixup() argument
28 uint32_t addr = rcar_pcie_base[controller]; in rcar_pcie_fixup()
34 if (cpg & (MSTP318 << !controller)) in rcar_pcie_fixup()
/arm-trusted-firmware-2.8.0/docs/plat/
A Dimx8.rst13 and 1 Cortex-M4 system controller.
16 controller.
20 controller is a Cortex-M4 that executes system controller firmware.
54 with certain offset for BOOT ROM. The system controller firmware,
A Drpi4.rst6 model has a GICv2 interrupt controller.
14 not seem to feature a secure memory controller of any kind, so portions of
62 This part knows how to access the MMC controller and how to parse a FAT
/arm-trusted-firmware-2.8.0/docs/components/
A Dindex.rst17 platform-interrupt-controller-API
A Dmpmm.rst25 external power controller can use these metrics to budget SoC power by
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A DREADME.odt8 | Configuration | |DRAM controller| Slot 1 | Slo…
/arm-trusted-firmware-2.8.0/docs/
A Dlicense.rst83 - ``include/dt-bindings/interrupt-controller/arm-gic.h``
84 - ``include/dt-bindings/interrupt-controller/irq.h``

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