| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | mt8183.rst | 5 The chip incorporates eight cores - four Cortex-A53 little cores and Cortex-A73.
|
| A D | mt8186.rst | 5 The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A76.
|
| A D | mt8192.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | mt8195.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
|
| A D | mt8188.rst | 5 The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A78.
|
| A D | nvidia-tegra.rst | 7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
13 eight cores if required.
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
30 heterogeneous multi-processing with all six cores if required.
33 fully Armv8-A architecture compatible. Each of the two Denver cores
37 cache, which services both cores.
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
|
| A D | rpi3.rst | 5 Arm Cortex-A53 cores.
25 card) and is located between all Arm cores and the DRAM. Check the `Raspberry Pi
30 the cores boot in AArch64 mode.
40 the cores are powered on at the same time and start at address **0x0**.
48 Ideally, we want to load the kernel and have all cores available, which means
49 that we need to make the secondary cores work in the way the kernel expects, as
50 explained in `Secondary cores`_. In practice, a small bootstrap is needed
89 All addresses are Physical Addresses from the point of view of the Arm cores.
162 Secondary cores
178 cold boot, all secondary cores wait in a loop until they are given given an
[all …]
|
| A D | brcm-stingray.rst | 6 Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores.
|
| A D | allwinner.rst | 5 SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
46 - ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown
55 - ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and
|
| A D | xilinx-zynqmp.rst | 72 The 4 leaf power domains represent the individual A53 cores, while resources
|
| A D | qti-msm8916.rst | 5 with four ARM Cortex-A53 cores. There are differents variants (MSM8916,
38 secondary CPU cores (PSCI ``CPU_ON``) is supported. Basic CPU core power
|
| /arm-trusted-firmware-2.8.0/docs/components/fconf/ |
| A D | amu-bindings.rst | 31 The ``amus`` node describes the |AMUs| implemented by the cores in the system.
38 registers of one or more |AMUs|, and may be shared by multiple cores.
73 An example system offering four cores made up of two clusters, where the cores
137 In this situation, ``cpu0`` and ``cpu1`` (the two cores in the first cluster),
139 ``cpu3`` (the two cores in the second cluster), share the view of their |AMUs|
|
| A D | mpmm-bindings.rst | 30 An example system offering two cores, one with support for |MPMM| and one
|
| /arm-trusted-firmware-2.8.0/include/lib/mpmm/ |
| A D | mpmm.h | 46 struct mpmm_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ member
|
| /arm-trusted-firmware-2.8.0/docs/components/ |
| A D | mpmm.rst | 5 some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
6 Cortex-A510 cores. This mechanism detects and limits high-activity events to
26 limiting the number of cores that can execute higher-activity workloads or
|
| /arm-trusted-firmware-2.8.0/include/lib/extensions/ |
| A D | amu.h | 35 struct amu_core cores[PLATFORM_CORE_COUNT]; /* Per-core data */ member
|
| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | arm_fpga.dts | 6 * Number and kind of CPU cores differs from image to image, so the
54 /* This node will be removed at runtime on cores without SPE. */
97 /* The GICR size will be adjusted at runtime to match the cores. */
|
| /arm-trusted-firmware-2.8.0/lib/fconf/ |
| A D | fconf_mpmm_getter.c | 39 core = &fconf_mpmm_topology.cores[core_pos]; in fconf_populate_mpmm_cpu()
|
| A D | fconf_amu_getter.c | 100 amu = &fconf_amu_topology_.cores[idx]; in fconf_populate_amu_cpu()
|
| /arm-trusted-firmware-2.8.0/lib/mpmm/ |
| A D | mpmm.c | 56 supported = topology->cores[core_pos].supported && in mpmm_supported()
|
| /arm-trusted-firmware-2.8.0/include/plat/arm/common/ |
| A D | fconf_ethosn_getter.h | 49 struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX]; member
|
| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | threat_model_fvp_r.rst | 35 v8-R64 cores do not support EL3, and (essentially) all operation is defined as
46 v8-R64 cores, running in EL2, use an MPU for memory management, rather than an
53 Another substantial difference between v8-A and v8-R64 cores is that v8-R64 does
|
| /arm-trusted-firmware-2.8.0/docs/plat/arm/arm_fpga/ |
| A D | index.rst | 5 testing and bringup of new cores. With that focus, peripheral support is
22 As the number and topology layout of the CPU cores differs significantly
32 internal list, but for new or experimental cores this creates a lot of
|
| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-9.rst | 50 TF-A using the loop workaround(all cores that implement FEAT_CSV2 except the
93 For all other cores impacted by Spectre-BHB, some of which that do not implement
|
| /arm-trusted-firmware-2.8.0/drivers/arm/ethosn/ |
| A D | ethosn_smc.c | 63 const struct ethosn_core_t *core = &(dev->cores[core_idx]); in ethosn_get_device_and_core()
|