Searched refs:ctl (Results 1 – 11 of 11) sorted by relevance
| /arm-trusted-firmware-2.8.0/drivers/st/ddr/ |
| A D | stm32mp_ddr.c | 23 return (uintptr_t)priv->ctl; in get_base_addr()
52 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl) in stm32mp_ddr_start_sw_done() argument
56 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); in stm32mp_ddr_start_sw_done()
60 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl) in stm32mp_ddr_wait_sw_done_ack() argument
67 (uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl)); in stm32mp_ddr_wait_sw_done_ack()
71 swstat = mmio_read_32((uintptr_t)&ctl->swstat); in stm32mp_ddr_wait_sw_done_ack()
73 (uintptr_t)&ctl->swstat, swstat); in stm32mp_ddr_wait_sw_done_ack()
80 (uintptr_t)&ctl->swstat, swstat); in stm32mp_ddr_wait_sw_done_ack()
83 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl) in stm32mp_ddr_enable_axi_port() argument
88 mmio_read_32((uintptr_t)&ctl->pctrl_0)); in stm32mp_ddr_enable_axi_port()
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| A D | stm32mp1_ddr.c | 353 (uintptr_t)&priv->ctl->mrctrl0, in stm32mp1_mode_register_write()
357 (uintptr_t)&priv->ctl->mrctrl1, in stm32mp1_mode_register_write()
395 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
456 (uintptr_t)&priv->ctl->pwrctl, in stm32mp1_ddr3_dll_off()
475 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr3_dll_off()
529 (uintptr_t)&priv->ctl->dbg1, in stm32mp1_ddr3_dll_off()
535 stm32mp_ddr_start_sw_done(ctl); in stm32mp1_refresh_disable()
548 stm32mp_ddr_start_sw_done(ctl); in stm32mp1_refresh_restore()
625 (uintptr_t)&priv->ctl->dfimisc, in stm32mp1_ddr_init()
638 (uintptr_t)&priv->ctl->mstr, in stm32mp1_ddr_init()
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| A D | stm32mp1_ram.c | 142 priv->ctl = (struct stm32mp_ddrctl *)stm32mp_ddrctrl_base(); in stm32mp1_ddr_probe()
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| /arm-trusted-firmware-2.8.0/bl32/tsp/ |
| A D | tsp_timer.c | 20 uint32_t ctl; member
31 uint32_t ctl = 0; in tsp_generic_timer_start() local
38 set_cntp_ctl_enable(ctl); in tsp_generic_timer_start()
39 write_cntps_ctl_el1(ctl); in tsp_generic_timer_start()
77 pcpu_timer_context[linear_id].ctl = read_cntps_ctl_el1(); in tsp_generic_timer_save()
90 write_cntps_ctl_el1(pcpu_timer_context[linear_id].ctl); in tsp_generic_timer_restore()
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| /arm-trusted-firmware-2.8.0/include/drivers/st/ |
| A D | stm32mp_ddr.h | 48 struct stm32mp_ddrctl *ctl; member
64 void stm32mp_ddr_start_sw_done(struct stm32mp_ddrctl *ctl);
65 void stm32mp_ddr_wait_sw_done_ack(struct stm32mp_ddrctl *ctl);
66 void stm32mp_ddr_enable_axi_port(struct stm32mp_ddrctl *ctl);
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| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | stm32mp15-ddr.dtsi | 11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
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| A D | stm32mp13-ddr.dtsi | 11 st,ctl-reg = <
39 st,ctl-timing = <
54 st,ctl-map = <
66 st,ctl-perf = <
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| /arm-trusted-firmware-2.8.0/plat/mediatek/mt8173/ |
| A D | plat_pm.c | 127 uint64_t ctl; in mt_save_generic_timer() local
133 : "=&r" (ctl), "=&r" (val) in mt_save_generic_timer()
140 : "=&r" (val), "=&r" (ctl) in mt_save_generic_timer()
147 : "=&r" (val), "=&r" (ctl) in mt_save_generic_timer()
154 uint64_t ctl; in mt_restore_generic_timer() local
160 : "=&r" (ctl), "=&r" (val) in mt_restore_generic_timer()
167 : "=&r" (val), "=&r" (ctl) in mt_restore_generic_timer()
174 : "=&r" (val), "=&r" (ctl) in mt_restore_generic_timer()
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| /arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/ |
| A D | suspend.c | 125 static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, in rkclk_ddr_reset() argument
129 ctl &= 0x1; in rkclk_ddr_reset()
132 CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/sd/ |
| A D | sd_mmc.h | 288 uint32_t ctl; /* Control register */ member
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| /arm-trusted-firmware-2.8.0/drivers/nxp/sd/ |
| A D | sd_mmc.c | 169 val = esdhc_in32(&mmc->esdhc_regs->ctl) | ESDHC_DCR_SNOOP; in esdhc_init()
170 esdhc_out32(&mmc->esdhc_regs->ctl, val); in esdhc_init()
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