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Searched refs:ctx (Results 1 – 25 of 66) sorted by relevance

123

/arm-trusted-firmware-2.8.0/drivers/nxp/crypto/caam/src/auth/
A Dhash.c48 *ctx = &glbl_ctx; in hash_init()
71 ctx->active = false; in hash_update()
78 ctx->active = false; in hash_update()
88 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, in hash_update()
91 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); in hash_update()
93 sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uintptr_t) data_ptr); in hash_update()
95 sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, in hash_update()
98 ctx->sg_num++; in hash_update()
129 final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) | in hash_final()
131 sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final); in hash_final()
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A Drsa.c41 struct rsa_context ctx __aligned(CACHE_WRITEBACK_GRANULE); in rsa_public_verif_sec()
47 memset(&ctx, 0, sizeof(struct rsa_context)); in rsa_public_verif_sec()
49 ctx.pkin.a = sign; in rsa_public_verif_sec()
50 ctx.pkin.a_siz = klen; in rsa_public_verif_sec()
51 ctx.pkin.n = rsa_pub_key; in rsa_public_verif_sec()
52 ctx.pkin.n_siz = klen; in rsa_public_verif_sec()
53 ctx.pkin.e = rsa_pub_key + klen; in rsa_public_verif_sec()
54 ctx.pkin.e_siz = klen; in rsa_public_verif_sec()
56 cnstr_jobdesc_pkha_rsaexp(jobdesc.desc, &ctx.pkin, to, klen); in rsa_public_verif_sec()
61 flush_dcache_range((uintptr_t)&ctx.pkin, sizeof(ctx.pkin)); in rsa_public_verif_sec()
/arm-trusted-firmware-2.8.0/lib/xlat_tables_v2/
A Dxlat_tables_core.c97 assert(ctx->next_table < ctx->tables_num); in xlat_table_get_empty()
99 return ctx->tables[ctx->next_table++]; in xlat_table_get_empty()
710 if (ctx->mmap[ctx->mmap_num - 1].size != 0U) in mmap_add_region_check()
777 const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num; in mmap_add_region_ctx()
1005 0U, ctx->base_table, ctx->base_table_entries, in mmap_add_dynamic_region_ctx()
1034 ctx->base_table, ctx->base_table_entries, in mmap_add_dynamic_region_ctx()
1119 xlat_tables_unmap_region(ctx, mm, 0U, ctx->base_table, in mmap_remove_dynamic_region_ctx()
1135 mm = ctx->mmap; in mmap_remove_dynamic_region_ctx()
1221 ctx->base_table, ctx->base_table_entries, in init_xlat_tables_ctx()
1238 assert(ctx->max_va <= ctx->va_max_address); in init_xlat_tables_ctx()
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A Dxlat_tables_utils.c244 ctx->base_table_entries); in xlat_tables_print()
259 xlat_tables_print_internal(ctx, 0U, ctx->base_table, in xlat_tables_print()
260 ctx->base_table_entries, ctx->base_level); in xlat_tables_print()
357 assert(ctx != NULL); in xlat_get_mem_attributes_internal()
358 assert(ctx->initialized); in xlat_get_mem_attributes_internal()
367 ctx->base_table, in xlat_get_mem_attributes_internal()
368 ctx->base_table_entries, in xlat_get_mem_attributes_internal()
392 xlat_desc_print(ctx, desc); in xlat_get_mem_attributes_internal()
452 assert(ctx != NULL); in xlat_change_mem_attributes_ctx()
453 assert(ctx->initialized); in xlat_change_mem_attributes_ctx()
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/arm-trusted-firmware-2.8.0/drivers/st/crypto/
A Dstm32_saes.c294 saes_write_key(ctx); in saes_prepare_key()
297 if ((IS_CHAINING_MODE(ECB, ctx->cr) || IS_CHAINING_MODE(CBC, ctx->cr)) && in saes_prepare_key()
332 ctx->cr = mmio_read_32(ctx->base + _SAES_CR); in save_context()
365 mmio_write_32(ctx->base + _SAES_CR, ctx->cr); in restore_context()
373 saes_write_iv(ctx); in restore_context()
433 ctx->assoc_len = 0U; in stm32_saes_init()
434 ctx->load_len = 0U; in stm32_saes_init()
642 saes_end(ctx, ret); in stm32_saes_update_assodata()
788 mmio_write_32(ctx->base + _SAES_DINR, ctx->assoc_len); in stm32_saes_final()
790 mmio_write_32(ctx->base + _SAES_DINR, ctx->load_len); in stm32_saes_final()
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/arm-trusted-firmware-2.8.0/lib/el3_runtime/aarch64/
A Dcontext_mgmt.c285 zeromem(ctx, sizeof(*ctx)); in setup_context_common()
430 assert(ctx != NULL); in cm_setup_context()
478 sme_enable(ctx); in manage_extensions_nonsecure()
481 sve_enable(ctx); in manage_extensions_nonsecure()
518 sme_enable(ctx); in manage_extensions_secure()
524 sme_disable(ctx); in manage_extensions_secure()
532 sve_enable(ctx); in manage_extensions_secure()
538 sve_disable(ctx); in manage_extensions_secure()
552 cpu_context_t *ctx; in cm_init_context_by_index() local
564 cpu_context_t *ctx; in cm_init_my_context() local
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/arm-trusted-firmware-2.8.0/plat/qti/qtiseclib/src/
A Dqtiseclib_cb_interface.c132 void *ctx; in qtiseclib_cb_get_ns_ctx() local
134 ctx = cm_get_context(NON_SECURE); in qtiseclib_cb_get_ns_ctx()
135 if (ctx) { in qtiseclib_cb_get_ns_ctx()
141 read_ctx_reg(get_el3state_ctx(ctx), CTX_SPSR_EL3); in qtiseclib_cb_get_ns_ctx()
145 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SPSR_EL1); in qtiseclib_cb_get_ns_ctx()
147 read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_ELR_EL1); in qtiseclib_cb_get_ns_ctx()
150 qti_ns_ctx->x0 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0); in qtiseclib_cb_get_ns_ctx()
151 qti_ns_ctx->x1 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1); in qtiseclib_cb_get_ns_ctx()
152 qti_ns_ctx->x2 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2); in qtiseclib_cb_get_ns_ctx()
153 qti_ns_ctx->x3 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3); in qtiseclib_cb_get_ns_ctx()
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/arm-trusted-firmware-2.8.0/services/std_svc/spmd/
A Dspmd_pm.c72 assert(ctx != NULL); in spmd_cpu_on_finish_handler()
73 assert(ctx->state != SPMC_STATE_ON); in spmd_cpu_on_finish_handler()
90 el3_state = get_el3state_ctx(&ctx->cpu_ctx); in spmd_cpu_on_finish_handler()
97 ctx->state = SPMC_STATE_ON_PENDING; in spmd_cpu_on_finish_handler()
99 rc = spmd_spm_core_sync_entry(ctx); in spmd_cpu_on_finish_handler()
103 ctx->state = SPMC_STATE_OFF; in spmd_cpu_on_finish_handler()
107 ctx->state = SPMC_STATE_ON; in spmd_cpu_on_finish_handler()
121 assert(ctx != NULL); in spmd_cpu_off_handler()
122 assert(ctx->state != SPMC_STATE_OFF); in spmd_cpu_off_handler()
128 rc = spmd_spm_core_sync_entry(ctx); in spmd_cpu_off_handler()
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/arm-trusted-firmware-2.8.0/lib/xlat_mpu/
A Dxlat_mpu_core.c181 if (ctx->mmap[ctx->mmap_num - 1].size != 0U) { in mmap_add_region_check()
250 const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num; in mmap_add_region_ctx()
262 assert(!ctx->initialized); in mmap_add_region_ctx()
274 mm_last = ctx->mmap; in mmap_add_region_ctx()
300 if (end_pa > ctx->max_pa) { in mmap_add_region_ctx()
301 ctx->max_pa = end_pa; in mmap_add_region_ctx()
304 ctx->max_va = end_va; in mmap_add_region_ctx()
322 assert(ctx != NULL); in init_xlat_tables_ctx()
323 assert(!ctx->initialized); in init_xlat_tables_ctx()
364 ctx->initialized = true; in init_xlat_tables_ctx()
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A Dxlat_mpu_utils.c32 void xlat_tables_print(__unused xlat_ctx_t *ctx) in xlat_tables_print() argument
39 static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx) in xlat_tables_print_internal() argument
78 void xlat_tables_print(__unused xlat_ctx_t *ctx) in xlat_tables_print() argument
80 xlat_tables_print_internal(ctx); in xlat_tables_print()
/arm-trusted-firmware-2.8.0/drivers/amlogic/crypto/
A Dsha_dma.c130 if (ctx->started == 0) { in asd_compute_sha()
132 ctx->started = 1; in asd_compute_sha()
136 ctx->started = 0; in asd_compute_sha()
157 if (ctx->blocksz) { in asd_sha_update()
159 memcpy(ctx->block + ctx->blocksz, data, nr); in asd_sha_update()
160 ctx->blocksz += nr; in asd_sha_update()
166 asd_compute_sha(ctx, ctx->block, SHA256_BLOCKSZ, 0); in asd_sha_update()
167 ctx->blocksz = 0; in asd_sha_update()
175 memcpy(ctx->block + ctx->blocksz, data, nr); in asd_sha_update()
176 ctx->blocksz += nr; in asd_sha_update()
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/arm-trusted-firmware-2.8.0/lib/cpus/aarch64/
A Dcpuamu.c32 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; in cpuamu_context_save() local
38 ctx->mask = cpuamu_read_cpuamcntenset_el0(); in cpuamu_context_save()
41 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_save()
46 ctx->cnts[i] = cpuamu_cnt_read(i); in cpuamu_context_save()
51 struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()]; in cpuamu_context_restore() local
60 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_restore()
65 cpuamu_cnt_write(i, ctx->cnts[i]); in cpuamu_context_restore()
69 cpuamu_write_cpuamcntenset_el0(ctx->mask); in cpuamu_context_restore()
/arm-trusted-firmware-2.8.0/lib/el3_runtime/aarch32/
A Dcontext_mgmt.c62 assert(ctx != NULL); in cm_setup_context()
67 zeromem(ctx, sizeof(*ctx)); in cm_setup_context()
69 reg_ctx = get_regs_ctx(ctx); in cm_setup_context()
160 cpu_context_t *ctx; in cm_init_context_by_index() local
162 cm_setup_context(ctx, ep); in cm_init_context_by_index()
172 cpu_context_t *ctx; in cm_init_my_context() local
174 cm_setup_context(ctx, ep); in cm_init_my_context()
188 cpu_context_t *ctx = cm_get_context(security_state); in cm_prepare_el3_exit() local
191 assert(ctx != NULL); in cm_prepare_el3_exit()
194 scr = read_ctx_reg(get_regs_ctx(ctx), CTX_SCR); in cm_prepare_el3_exit()
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/arm-trusted-firmware-2.8.0/services/spd/trusty/
A Dtrusty.c159 ctx->fiq_handler_active = 1; in trusty_fiq_handler()
160 (void)memcpy(&ctx->fiq_gpregs, get_gpregs_ctx(handle), sizeof(ctx->fiq_gpregs)); in trusty_fiq_handler()
166 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_handler_pc, (uint32_t)ctx->fiq_handler_cpsr); in trusty_fiq_handler()
174 struct trusty_cpu_ctx *ctx; in trusty_set_fiq_handler() local
181 ctx = &trusty_cpu_ctx[cpu]; in trusty_set_fiq_handler()
184 ctx->fiq_handler_sp = stack; in trusty_set_fiq_handler()
194 SMC_RET4(handle, ctx->fiq_pc, ctx->fiq_cpsr, sp_el0, ctx->fiq_sp_el1); in trusty_get_fiq_regs()
222 (void)memcpy(get_gpregs_ctx(handle), &ctx->fiq_gpregs, sizeof(ctx->fiq_gpregs)); in trusty_fiq_exit()
223 ctx->fiq_handler_active = 0; in trusty_fiq_exit()
225 cm_set_elr_spsr_el3(NON_SECURE, ctx->fiq_pc, (uint32_t)ctx->fiq_cpsr); in trusty_fiq_exit()
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/arm-trusted-firmware-2.8.0/include/drivers/amlogic/crypto/
A Dsha_dma.h26 static inline void asd_sha_init(struct asd_ctx *ctx, enum ASD_MODE mode) in asd_sha_init() argument
28 ctx->started = 0; in asd_sha_init()
29 ctx->mode = mode; in asd_sha_init()
30 ctx->blocksz = 0; in asd_sha_init()
33 void asd_sha_update(struct asd_ctx *ctx, void *data, size_t len);
34 void asd_sha_finalize(struct asd_ctx *ctx);
/arm-trusted-firmware-2.8.0/services/std_svc/drtm/
A Ddrtm_remediation.c17 uint64_t drtm_set_error(uint64_t x1, void *ctx) in drtm_set_error() argument
24 SMC_RET1(ctx, INTERNAL_ERROR); in drtm_set_error()
27 SMC_RET1(ctx, SUCCESS); in drtm_set_error()
30 uint64_t drtm_get_error(void *ctx) in drtm_get_error() argument
38 SMC_RET1(ctx, INTERNAL_ERROR); in drtm_get_error()
41 SMC_RET2(ctx, SUCCESS, error_code); in drtm_get_error()
/arm-trusted-firmware-2.8.0/services/std_svc/spm/spm_mm/
A Dspm_mm_main.c93 assert(ctx != NULL); in spm_sp_synchronous_entry()
96 cm_set_context(&(ctx->cpu_ctx), SECURE); in spm_sp_synchronous_entry()
121 sp_context_t *ctx = &sp_ctx; in spm_sp_synchronous_exit() local
139 sp_context_t *ctx; in spm_init() local
143 ctx = &sp_ctx; in spm_init()
145 ctx->state = SP_STATE_RESET; in spm_init()
147 rc = spm_sp_synchronous_entry(ctx); in spm_init()
150 ctx->state = SP_STATE_IDLE; in spm_init()
162 sp_context_t *ctx; in spm_mm_setup() local
170 ctx = &sp_ctx; in spm_mm_setup()
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A Dspm_mm_setup.c29 cpu_context_t *ctx = &(sp_ctx->cpu_ctx); in spm_sp_setup() local
67 cm_setup_context(ctx, &ep_info); in spm_sp_setup()
74 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_SP_EL0, in spm_sp_setup()
125 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_MAIR_EL1, in spm_sp_setup()
128 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TCR_EL1, in spm_sp_setup()
131 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_TTBR0_EL1, in spm_sp_setup()
135 u_register_t sctlr_el1 = read_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1); in spm_sp_setup()
171 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); in spm_sp_setup()
179 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_VBAR_EL1, in spm_sp_setup()
182 write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_CNTKCTL_EL1, in spm_sp_setup()
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/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch64/
A Damu.c239 ctx_write_cptr_el3_tam(ctx, 0U); in amu_enable()
304 ctx_write_scr_el3_amvoffen(ctx, 1U); in amu_enable()
461 struct amu_ctx *ctx; in amu_context_save() local
479 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
496 write_amcntenclr0_el0_px(ctx->group0_enable); in amu_context_save()
501 write_amcntenclr1_el0_px(ctx->group1_enable); in amu_context_save()
512 ctx->group0_cnts[i] = amu_group0_cnt_read(i); in amu_context_save()
517 ctx->group1_cnts[i] = amu_group1_cnt_read(i); in amu_context_save()
553 struct amu_ctx *ctx; in amu_context_restore() local
573 ctx = &amu_ctxs_[core_pos]; in amu_context_restore()
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/arm-trusted-firmware-2.8.0/services/std_svc/rmmd/
A Drmmd_main.c97 assert(cm_get_context(REALM) == &(ctx->cpu_ctx)); in rmmd_rmm_sync_exit()
104 rmmd_rmm_exit(ctx->c_rt_ctx, rc); in rmmd_rmm_sync_exit()
126 sve_enable(ctx); in manage_extensions_realm()
131 sve_disable(ctx); in manage_extensions_realm()
146 manage_extensions_realm(&ctx->cpu_ctx); in rmm_init()
151 rc = rmmd_rmm_sync_entry(ctx); in rmm_init()
269 SMC_RET8(ctx, x0, x1, x2, x3, x4, in rmmd_smc_forward()
275 SMC_RET5(ctx, x0, x1, x2, x3, x4); in rmmd_smc_forward()
359 cm_setup_context(&ctx->cpu_ctx, rmm_ep_info); in rmmd_cpu_on_finish_handler()
362 manage_extensions_realm(&ctx->cpu_ctx); in rmmd_cpu_on_finish_handler()
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/arm-trusted-firmware-2.8.0/plat/imx/common/
A Dplat_imx8_gic.c100 void plat_gic_save(unsigned int proc_num, struct plat_gic_ctx *ctx) in plat_gic_save() argument
104 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); in plat_gic_save()
105 gicv3_distif_save(&ctx->dist_ctx); in plat_gic_save()
108 void plat_gic_restore(unsigned int proc_num, struct plat_gic_ctx *ctx) in plat_gic_restore() argument
111 gicv3_distif_init_restore(&ctx->dist_ctx); in plat_gic_restore()
113 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); in plat_gic_restore()
/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32_saes.h49 int stm32_saes_init(struct stm32_saes_context *ctx, bool is_decrypt,
52 int stm32_saes_update(struct stm32_saes_context *ctx, bool last_block,
54 int stm32_saes_update_assodata(struct stm32_saes_context *ctx, bool last_block,
56 int stm32_saes_update_load(struct stm32_saes_context *ctx, bool last_block,
58 int stm32_saes_final(struct stm32_saes_context *ctx, uint8_t *tag, size_t tag_len);
/arm-trusted-firmware-2.8.0/include/lib/el3_runtime/aarch64/
A Dcontext.h400 #define read_ctx_reg(ctx, offset) ((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) argument
401 #define write_ctx_reg(ctx, offset, val) (((ctx)->ctx_regs[(offset) >> DWORD_SHIFT]) \ argument
473 #define set_aapcs_args0(ctx, x0) do { \ argument
476 #define set_aapcs_args1(ctx, x0, x1) do { \ argument
478 set_aapcs_args0(ctx, x0); \
480 #define set_aapcs_args2(ctx, x0, x1, x2) do { \ argument
482 set_aapcs_args1(ctx, x0, x1); \
486 set_aapcs_args2(ctx, x0, x1, x2); \
490 set_aapcs_args3(ctx, x0, x1, x2, x3); \
494 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
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/arm-trusted-firmware-2.8.0/tools/encrypt_fw/src/
A Dencrypt.c28 EVP_CIPHER_CTX *ctx; in gcm_encrypt() local
79 ctx = EVP_CIPHER_CTX_new(); in gcm_encrypt()
80 if (ctx == NULL) { in gcm_encrypt()
86 ret = EVP_EncryptInit_ex(ctx, EVP_aes_256_gcm(), NULL, NULL, NULL); in gcm_encrypt()
93 ret = EVP_EncryptInit_ex(ctx, NULL, NULL, key, iv); in gcm_encrypt()
100 ret = EVP_EncryptUpdate(ctx, enc_data, &enc_len, data, bytes); in gcm_encrypt()
110 ret = EVP_EncryptFinal_ex(ctx, enc_data, &enc_len); in gcm_encrypt()
117 ret = EVP_CIPHER_CTX_ctrl(ctx, EVP_CTRL_GCM_GET_TAG, TAG_SIZE, tag); in gcm_encrypt()
141 EVP_CIPHER_CTX_free(ctx); in gcm_encrypt()
/arm-trusted-firmware-2.8.0/lib/extensions/amu/aarch32/
A Damu.c291 struct amu_ctx *ctx; in amu_context_save() local
307 ctx = &amu_ctxs_[core_pos]; in amu_context_save()
320 ctx->group0_enable = read_amcntenset0_px(); in amu_context_save()
321 write_amcntenclr0_px(ctx->group0_enable); in amu_context_save()
325 ctx->group1_enable = read_amcntenset1_px(); in amu_context_save()
326 write_amcntenclr1_px(ctx->group1_enable); in amu_context_save()
337 ctx->group0_cnts[i] = amu_group0_cnt_read(i); in amu_context_save()
354 struct amu_ctx *ctx; in amu_context_restore() local
371 ctx = &amu_ctxs_[core_pos]; in amu_context_restore()
409 write_amcntenset0_px(ctx->group0_enable); in amu_context_restore()
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