Searched refs:divider (Results 1 – 6 of 6) sorted by relevance
41 uint32_t divider = plat_get_syscnt_freq2(); in tegra_delay_timer_init() local44 while (((multiplier % 10U) == 0U) && ((divider % 10U) == 0U)) { in tegra_delay_timer_init()46 divider /= 10U; in tegra_delay_timer_init()55 tegra_timer_ops.clk_div = divider; in tegra_delay_timer_init()
145 static unsigned int pl011_freq_from_divider(unsigned int divider) in pl011_freq_from_divider() argument149 freq = divider * FPGA_DEFAULT_BAUDRATE * PL011_OVERSAMPLING; in pl011_freq_from_divider()182 unsigned int divider; in fpga_get_system_frequency() local187 divider = mmio_read_32(pl011_base + UARTIBRD); in fpga_get_system_frequency()188 divider <<= PL011_FRAC_SHIFT; in fpga_get_system_frequency()189 divider += mmio_read_32(pl011_base + UARTFBRD); in fpga_get_system_frequency()195 return round_multiple(pl011_freq_from_divider(divider), in fpga_get_system_frequency()
729 const struct div_cfg *divider = &priv->div[div_id]; in clk_stm32_div_get_value() local732 val = mmio_read_32(priv->base + divider->offset) >> divider->shift; in clk_stm32_div_get_value()733 val &= clk_div_mask(divider->width); in clk_stm32_div_get_value()742 const struct div_cfg *divider = &priv->div[div_id]; in _clk_stm32_divider_recalc() local746 div = _get_div(divider->table, val, divider->flags, divider->width); in _clk_stm32_divider_recalc()769 const struct div_cfg *divider; in clk_stm32_set_div() local778 divider = &priv->div[div_id]; in clk_stm32_set_div()779 address = priv->base + divider->offset; in clk_stm32_set_div()781 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); in clk_stm32_set_div()784 if (divider->bitrdy == DIV_NO_BIT_RDY) { in clk_stm32_set_div()[all …]
1193 uint32_t divider) in pm_clock_setdivider() argument1206 return pm_pll_set_parameter(nid, PM_PLL_PARAM_FBDIV, divider); in pm_clock_setdivider()1215 if (div0 == (divider & div0)) { in pm_clock_setdivider()1217 val = divider & ~div0; in pm_clock_setdivider()1218 } else if (div1 == (divider & div1)) { in pm_clock_setdivider()1220 val = (divider & ~div1) >> 16; in pm_clock_setdivider()1241 uint32_t *divider) in pm_clock_getdivider() argument1251 return pm_pll_get_parameter(nid, PM_PLL_PARAM_FBDIV, divider); in pm_clock_getdivider()1268 *divider = val; in pm_clock_getdivider()1279 *divider |= val << 16; in pm_clock_getdivider()
141 uint32_t divider);143 uint32_t *divider);
1020 …- implement timer init divider via cpu frequency. ([#1](https://review.trustedfirmware.org:29418/T…
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