Searched refs:dwc_ddrphy_apb_wr (Results 1 – 3 of 3) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/ddr/ |
| A D | dram_retention.c | 74 dwc_ddrphy_apb_wr(0xd0000, 0x0); in dram_enter_retention()
78 dwc_ddrphy_apb_wr(0xd0000, 0x1); in dram_enter_retention()
161 dwc_ddrphy_apb_wr(0xd0000, 0x0); in dram_exit_retention()
165 dwc_ddrphy_apb_wr(0xd0000, 0x1); in dram_exit_retention()
198 dwc_ddrphy_apb_wr(0xd0000, 0x0); in dram_exit_retention()
202 dwc_ddrphy_apb_wr(0xd0000, 0x1); in dram_exit_retention()
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| A D | dram.c | 71 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
78 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
85 dwc_ddrphy_apb_wr(cfg->reg, cfg->val); in dram_phy_init()
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| /arm-trusted-firmware-2.8.0/plat/imx/imx8m/include/ |
| A D | ddrc.h | 334 #define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IMX_DDRPHY_BASE + 4 * (addr), val) macro
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