Home
last modified time | relevance | path

Searched refs:freq (Results 1 – 25 of 39) sorted by relevance

12

/arm-trusted-firmware-2.8.0/drivers/renesas/common/emmc/
A Demmc_mount.c237 freq = MMC_52MHZ; in emmc_high_speed()
239 freq = MMC_26MHZ; in emmc_high_speed()
241 freq = MMC_20MHZ; in emmc_high_speed()
244 if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) { in emmc_high_speed()
520 *freq = MMC_52MHZ; in emmc_calc_tran_speed()
522 *freq = MMC_26MHZ; in emmc_calc_tran_speed()
524 *freq = MMC_20MHZ; in emmc_calc_tran_speed()
526 *freq = MMC_400KHZ; in emmc_calc_tran_speed()
536 switch (freq) { in emmc_set_timeout_register_value()
608 if (freq == NULL) { in emmc_set_request_mmc_clock()
[all …]
A Demmc_utility.c195 uint32_t freq; in emmc_send_idle_cmd() local
219 freq = MMC_400KHZ; in emmc_send_idle_cmd()
220 result = emmc_set_request_mmc_clock(&freq); in emmc_send_idle_cmd()
A Demmc_def.h40 EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq);
/arm-trusted-firmware-2.8.0/drivers/renesas/common/delay/
A Dmicro_delay.c20 uint64_t freq; in rcar_micro_delay() local
25 freq = read_cntfrq_el0(); in rcar_micro_delay()
29 wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq; in rcar_micro_delay()
/arm-trusted-firmware-2.8.0/plat/mediatek/mt8195/drivers/apusys/
A Dapupwr_clkctl.c115 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain) in apupwr_smc_acc_set_parent() argument
121 if (freq > DVFS_FREQ_ACC_APUPLL) { in apupwr_smc_acc_set_parent()
122 ERROR("%s wrong clksrc: %d\n", __func__, freq); in apupwr_smc_acc_set_parent()
143 switch (freq) { in apupwr_smc_acc_set_parent()
192 __func__, freq); in apupwr_smc_acc_set_parent()
200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate() argument
205 if (freq > DVFS_FREQ_MAX) { in apupwr_smc_pll_set_rate()
206 ERROR("%s wrong freq: %d\n", __func__, freq); in apupwr_smc_pll_set_rate()
251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
307 __func__, __LINE__, domain, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
A Dapupwr_clkctl.h15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
22 enum pll_set_rate_mode mode, int32_t freq);
A Dapupll.c238 static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq) in _cal_pll_data() argument
243 vco = freq; in _cal_pll_data()
508 enum pll_set_rate_mode mode, int32_t freq) in anpu_pll_set_rate() argument
519 _cal_pll_data(&pd, &dds, freq / 1000); in anpu_pll_set_rate()
522 __func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode); in anpu_pll_set_rate()
/arm-trusted-firmware-2.8.0/plat/arm/board/arm_fpga/
A Dfpga_bl31_setup.c147 unsigned int freq; in pl011_freq_from_divider() local
149 freq = divider * FPGA_DEFAULT_BAUDRATE * PL011_OVERSAMPLING; in pl011_freq_from_divider()
151 return freq >> PL011_FRAC_SHIFT; in pl011_freq_from_divider()
171 uint32_t freq; in fpga_get_system_frequency() local
173 err = fdt_read_uint32(fdt, node, "clock-frequency", &freq); in fpga_get_system_frequency()
175 return freq; in fpga_get_system_frequency()
217 static void fpga_dtb_update_clock(void *fdt, unsigned int freq) in fpga_dtb_update_clock() argument
219 uint32_t freq_dtb = fdt32_to_cpu(freq); in fpga_dtb_update_clock()
/arm-trusted-firmware-2.8.0/fdts/
A Dfvp-ve-Cortex-A5x1.dts84 freq-range = <50000000 100000000>;
93 freq-range = <5000000 50000000>;
102 freq-range = <80000000 120000000>;
111 freq-range = <23750000 165000000>;
120 freq-range = <80000000 80000000>;
129 freq-range = <25000000 60000000>;
/arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/
A Dhisi_dvfs.c41 unsigned int freq; member
48 unsigned int freq; member
55 unsigned int freq; member
234 if (acpu_dvfs_profile[tar_prof].freq > 800000) { in acpu_dvfs_freq_ascend()
387 if (acpu_dvfs_profile[tar_prof].freq > 800000) in acpu_dvfs_freq_ascend()
452 if (acpu_dvfs_profile[tar_prof].freq > 800000) { in acpu_dvfs_freq_descend()
534 if (acpu_dvfs_profile[tar_prof].freq > 800000) in acpu_dvfs_freq_descend()
671 if (max_freq == hi6220_acpu_profile[i].freq) { in acpu_dvfs_set_freq()
A Dhikey_ddr.c1085 static void ddrc_common_init(int freq) in ddrc_common_init() argument
1108 if (freq == DDR_FREQ_800M) in ddrc_common_init()
1109 mmio_write_32((0xf7128000 + 0x240), 167 * (freq / 2) / 1024); in ddrc_common_init()
1111 mmio_write_32((0xf7128000 + 0x240), 167 * freq / 1024); in ddrc_common_init()
1296 int lpddr3_freq_init(int freq) in lpddr3_freq_init() argument
1300 if (freq > DDR_FREQ_150M) { in lpddr3_freq_init()
1306 if (freq > DDR_FREQ_266M) { in lpddr3_freq_init()
1312 if (freq > DDR_FREQ_400M) { in lpddr3_freq_init()
1318 if (freq > DDR_FREQ_533M) { in lpddr3_freq_init()
1327 static void init_ddr(int freq) in init_ddr() argument
[all …]
/arm-trusted-firmware-2.8.0/plat/renesas/common/aarch64/
A Dplatform_common.c205 unsigned int freq; in plat_get_syscnt_freq2() local
207 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
208 if (freq == 0) in plat_get_syscnt_freq2()
211 return freq; in plat_get_syscnt_freq2()
/arm-trusted-firmware-2.8.0/include/drivers/st/
A Dstm32mp_clkfunc.h16 int fdt_osc_read_freq(const char *name, uint32_t *freq);
A Dbsec.h77 uint8_t freq; /* member
/arm-trusted-firmware-2.8.0/drivers/st/clk/
A Dstm32mp_clkfunc.c26 int fdt_osc_read_freq(const char *name, uint32_t *freq) in fdt_osc_read_freq() argument
59 *freq = fdt32_to_cpu(*cuint); in fdt_osc_read_freq()
66 *freq = 0; in fdt_osc_read_freq()
/arm-trusted-firmware-2.8.0/plat/imx/imx7/common/
A Dimx7_bl2_el3_common.c124 unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; in imx7_setup_system_counter() local
127 write_cntfrq(freq); in imx7_setup_system_counter()
/arm-trusted-firmware-2.8.0/drivers/st/mmc/
A Dstm32_sdmmc2.c164 uint32_t freq = STM32MP_MMC_INIT_FREQ; in stm32_sdmmc2_init() local
169 freq = MIN(sdmmc2_params.max_freq, freq); in stm32_sdmmc2_init()
197 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); in stm32_sdmmc2_init()
475 uint32_t clock_div, max_freq, freq; in stm32_sdmmc2_set_ios() local
508 freq = MIN(sdmmc2_params.max_freq, max_freq); in stm32_sdmmc2_set_ios()
510 freq = max_freq; in stm32_sdmmc2_set_ios()
513 clock_div = div_round_up(clk_rate, freq * 2U); in stm32_sdmmc2_set_ios()
/arm-trusted-firmware-2.8.0/drivers/nxp/ddr/nxp-ddr/
A Dregs.c367 rc0a = freq > 3200U ? 7U : in cal_ddr_sdram_rcw()
368 (freq > 2933U ? 6U : in cal_ddr_sdram_rcw()
369 (freq > 2666U ? 5U : in cal_ddr_sdram_rcw()
370 (freq > 2400U ? 4U : in cal_ddr_sdram_rcw()
371 (freq > 2133U ? 3U : in cal_ddr_sdram_rcw()
372 (freq > 1866U ? 2U : in cal_ddr_sdram_rcw()
373 (freq > 1600U ? 1U : 0U)))))); in cal_ddr_sdram_rcw()
374 rc0f = freq > 3200U ? 3U : in cal_ddr_sdram_rcw()
375 (freq > 2400U ? 2U : in cal_ddr_sdram_rcw()
376 (freq > 2133U ? 1U : 0U)); in cal_ddr_sdram_rcw()
[all …]
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/drivers/include/
A Dmce_private.h159 uint32_t freq,
233 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
255 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
/arm-trusted-firmware-2.8.0/drivers/mentor/i2c/
A Dmi2cv.c245 unsigned int n, m, freq, margin, min_margin = 0xffffffff; in mentor_i2c_bus_speed_set() local
252 freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); in mentor_i2c_bus_speed_set()
253 val = requested_speed - freq; in mentor_i2c_bus_speed_set()
256 if ((freq <= requested_speed) && in mentor_i2c_bus_speed_set()
/arm-trusted-firmware-2.8.0/plat/nvidia/tegra/soc/t186/drivers/mce/
A Dnvg.c233 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) in nvg_cc3_ctrl() argument
249 val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ in nvg_cc3_ctrl()
/arm-trusted-firmware-2.8.0/plat/imx/common/
A Dimx_sip_handler.c58 static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq) in imx_cpufreq_set_target() argument
60 sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq; in imx_cpufreq_set_target()
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/dram/
A Ddfs.c49 uint32_t freq; member
494 tmp = ((700000 + 10) * timing_config->freq + in gen_rk3399_ctl_params_f0()
640 if (timing_config->freq < 400) in gen_rk3399_ctl_params_f0()
715 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { in gen_rk3399_ctl_params_f0()
728 if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) && in gen_rk3399_ctl_params_f0()
889 if (timing_config->freq < 400) in gen_rk3399_ctl_params_f1()
965 if (timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) { in gen_rk3399_ctl_params_f1()
1521 if (timing_config->freq > 400) in gen_rk3399_phy_params()
1985 rk3399_dram_status.timing_config.freq = mhz; in prepare_ddr_timing()
2071 rk3399_suspend_status.freq = mhz; in ddr_prepare_for_sys_suspend()
[all …]
/arm-trusted-firmware-2.8.0/plat/ti/k3/common/drivers/ti_sci/
A Dti_sci.h138 int ti_sci_clock_get_freq(uint32_t dev_id, uint8_t clk_id, uint64_t *freq);
/arm-trusted-firmware-2.8.0/plat/rockchip/rk3399/drivers/soc/
A Dsoc.h130 uint32_t freq; member

Completed in 50 milliseconds

12