/arm-trusted-firmware-2.8.0/lib/zlib/ |
A D | inffast.c | 199 from = window; 201 from += wsize - op; 218 from = window; 240 *out++ = *from++; 241 *out++ = *from++; 242 *out++ = *from++; 246 *out++ = *from++; 254 *out++ = *from++; 255 *out++ = *from++; 256 *out++ = *from++; [all …]
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/arm-trusted-firmware-2.8.0/include/lib/libc/ |
A D | stdarg.h | 17 #define va_copy(to, from) __builtin_va_copy(to, from) argument
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/arm-trusted-firmware-2.8.0/docs/resources/diagrams/plantuml/ |
A D | fconf_bl1_load_config.puml | 38 load and auth image from fip 39 with info from plat_io_policy 46 note over fconf : get fw_config_dtb from image_info 58 load and auth image from fip 59 with info from plat_io_policy 66 note over fconf : get tb_fw_config_dtb from image_info
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A D | fconf_bl2_populate.puml | 32 note over fconf_dyn_cfg_getter: read dtb_registry properties from dtb 39 note over fconf_tbbr_getter: read tbbr properties from dtb 41 note over arm_fconf_io: read arm io propeties from dtb
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/arm-trusted-firmware-2.8.0/docs/plat/arm/tc/ |
A D | index.rst | 7 to abstract power and system management tasks away from application 9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access 28 The execution begins from SCP_BL1. SCP_BL1 powers up the AP which starts 29 executing AP_BL1 and then executes AP_BL2 which loads the SCP_BL2 from 31 is communicated to SCP using SDS. SCP copies SCP_BL2 from SRAM to its own
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/arm-trusted-firmware-2.8.0/docs/plat/ |
A D | rockchip.rst | 4 Trusted Firmware-A supports a number of Rockchip ARM SoCs from both 24 BL1/2 and BL33 can currently be supplied from either: 34 these images need to get build from the TF-A repository. 44 Both need replacing the PLAT argument with the platform from above you
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A D | rpi4.rst | 13 which is available from both the Non-secure and Secure worlds. The SoC does 15 DRAM can't be protected properly from the Non-secure world. 48 see some text from BL31, followed by the output of the EL2 payload. 49 The command line provided is read from the ``cmdline.txt`` file on the SD card. 55 port, also it deviates quite a lot from the RPi3 port in many other ways. 61 (bootcode.bin) from flash (EEPROM), which is again GPU code. 64 from the first FAT partition on the SD card.
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A D | meson-axg.rst | 12 can't be turned off, so there is a workaround to hide this from the caller. 25 by the one built from this port.
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A D | meson-g12a.rst | 12 can't be turned off, so there is a workaround to hide this from the caller. 24 mentioned **bl31.img** by the one built from this port.
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A D | meson-gxbb.rst | 12 can't be turned off, so there is a workaround to hide this from the caller. 24 by the one built from this port.
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A D | meson-gxl.rst | 12 can't be turned off, so there is a workaround to hide this from the caller. 24 mentioned **bl31.img** by the one built from this port.
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A D | qti.rst | 12 BL1/2 and BL33 can currently be supplied from Coreboot + Depthcharge 27 Coreboot, so only bl31.elf need to get build from the TF-A repository.
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/arm-trusted-firmware-2.8.0/docs/getting_started/ |
A D | docs-build.rst | 56 Documents can be built into HTML-formatted pages from project root directory by 63 Output from the build process will be placed in: 72 the command is run from the project root directory, as that would invoke the 79 Building rendered documentation from a container 87 from project root directory 95 The above command fetches the ``sphinxdoc/sphinx`` container from `docker 97 creates the documentation. Once done, exit the container and output from the
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A D | prerequisites.rst | 8 different from those listed below, however only the software described in this 29 - GCC >= 11.3.Rel1 (from the `Arm Developer website`_) 67 If using OpenSSL 3, older Linux versions may require it to be built from 113 appropriate version of Node.js, run the following **from the root directory of 126 TF-A has been tested with pre-built binaries and file systems from `Linaro 127 Release 20.01`_. Alternatively, you can build the binaries from source using 136 TrustedFirmware.org. To clone this repository from the server, run the following 155 running from within your newly-cloned repository:
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/arm-trusted-firmware-2.8.0/services/std_svc/spm/spm_mm/ |
A D | spm_mm_main.c | 47 void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) in sp_state_wait_switch() argument 54 if (sp_ptr->state == from) { in sp_state_wait_switch() 68 int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to) in sp_state_try_switch() argument 74 if (sp_ptr->state == from) { in sp_state_try_switch()
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/arm-trusted-firmware-2.8.0/docs/security_advisories/ |
A D | security-advisory-tfv-2.rst | 28 entrypoint code, which enables debug exceptions from the secure world. This can 35 from the secure world. 43 meaning that debug exceptions from Secure EL1 are enabled by the authentication 50 from AArch32 Secure EL1.
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A D | security-advisory-tfv-8.rst | 5 | Title | Not saving x0 to x3 registers can leak information from one | 18 | Impact | Leakage of SMC return values from one normal world SMC | 37 called. It restores the values of all general purpose registers taken from the 45 * This function restores all general purpose registers except x30 from the 58 some of the return values from one client to another. For example, if a victim 65 software must trap SMC calls from EL1 software to ensure secure behaviour.
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/arm-trusted-firmware-2.8.0/docs/components/measured_boot/ |
A D | event_log.rst | 6 from common code. 26 Note. Currently OP-TEE does not support reading DTBs from Secure memory
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/arm-trusted-firmware-2.8.0/docs/design/ |
A D | trusted-board-boot.rst | 4 The Trusted Board Boot (TBB) feature prevents malicious firmware from running on 44 with the hash extracted from the content certificate. Various hash algorithms 143 read from the verified certificate. A hash of that key is calculated and 145 registers. If they match, the BL2 hash is read from the certificate. 152 read from the certificate. Control is transferred to the BL2 image if all 156 read from the verified certificate. A hash of that key is calculated and 159 non-trusted world public keys from the verified certificate. 167 verification succeeds, BL2 reads and saves the BL3x public key from the 172 BL2 reads and saves the BL3x image hash from the certificate. 177 verification succeeds, BL2 reads and saves the BL33 public key from the [all …]
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A D | auth-framework.rst | 214 will have been extracted from the parent image i.e. BL31 content 283 parameters should be obtained from the parent image using the IPM. 457 parameter should be extracted from an image. 464 obtained from the parent image. 593 from the current image once it has been verified. 688 - ``data``: data to be hashed (obtained from current image) 689 - ``hash``: reference hash (obtained from parent image) 696 - ``pk``: the public key (obtained from parent image) 865 the signature from the certificate. 867 extract the signature algorithm from the certificate. [all …]
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/arm-trusted-firmware-2.8.0/docs/plat/arm/fvp_r/ |
A D | index.rst | 21 The execution begins from BL1 which loads the BL33 image, a boot-wrapped (bootloader + Operating Sy… 22 Operating System, from FIP to DRAM.
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/arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/ |
A D | porting.rst | 14 - The build system will reuse all files from within the soc directory, and take only the porting 15 files from the customer platform directory. 46 Boot rom can skip the current image and choose to boot from next position if a 48 feature is used for boot loader recovery by booting from a valid flash-image 77 skip image request message is printed on the screen and boot rom boots from the 88 The DDR driver called mv_ddr is released separately apart from TF-A sources. 118 board type, it is because the lanes from comphy-x to some PHY may have 119 different HW characteristic than lanes from comphy-y to the same
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/arm-trusted-firmware-2.8.0/docs/components/ |
A D | arm-sip-service.rst | 8 instruction executed from Exception Levels below EL3. SMC calls for SiP 37 switch its execution state (a.k.a. Register Width), either from AArch64 to 38 AArch32, or from AArch32 to AArch64, for the calling CPU. This service is only 62 Execution State has been switched. When calling from AArch64, *PC hi* must be 0. 66 0 and 1, respectively. When calling from AArch64, *Cookie hi* must be 0. 75 CPU endianness, however, is preserved from the previous execution state. Note 256 This operation reads a number of bytes from a file descriptor obtained by 272 On success, the read data is retrieved from the shared buffer after the 326 Create a link from `oldpath` to `newpath`.
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A D | ras.rst | 9 paradigm for handling platform errors: exceptions resulting from errors in 25 exceptions resulting from platform errors in EL3. It allows the platform to 35 error record registers from Non-secure. 47 Uncontainable Errors, Double Fault, and errors rising from EL3 execution. Please 67 continuous records from that index; 76 macros create a structure of type ``struct err_record_info`` from its arguments, 100 information resulting from probe to the error handler (see `below`__). For 114 ``cookie``, and ``handle`` parameters from the :ref:`top-level exception handler 194 Enabling RAS support is a platform choice constructed from three distinct, but 203 resulting from errors in NS world, to EL3. [all …]
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/arm-trusted-firmware-2.8.0/docs/process/ |
A D | coding-guidelines.rst | 276 - Secure world receives SMC from normal world with bad arguments. 277 - Secure world receives SMC from normal world at an unexpected time. 278 - BL31 receives SMC from BL32 with bad arguments. 279 - BL31 receives SMC from BL32 at unexpected time. 280 - Secure world receives recoverable error from hardware device. Retrying the 288 In some cases it may not be possible for the secure world to recover from an 309 - BL32 receives an unexpected SMC response from BL31 that it is unable to 310 recover from. 329 If the secure world is waiting for a response from an external source (for 333 the system from executing in this state indefinitely. [all …]
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