| /arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/ |
| A D | gicv2_main.c | 40 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_enable()
51 gicc_write_ctlr(driver_data->gicc_base, val); in gicv2_cpuif_enable()
63 assert(driver_data->gicc_base != 0U); in gicv2_cpuif_disable()
134 assert(plat_driver_data->gicc_base != 0U); in gicv2_driver_init()
183 assert(driver_data->gicc_base != 0U); in gicv2_is_fiq_enabled()
200 assert(driver_data->gicc_base != 0U); in gicv2_get_pending_interrupt_type()
215 assert(driver_data->gicc_base != 0U); in gicv2_get_pending_interrupt_id()
237 assert(driver_data->gicc_base != 0U); in gicv2_acknowledge_interrupt()
249 assert(driver_data->gicc_base != 0U); in gicv2_end_of_interrupt()
284 assert(driver_data->gicc_base != 0U); in gicv2_get_running_priority()
[all …]
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ |
| A D | soc.c | 349 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
361 *gicc_base = NXP_GICC_4K_ADDR; in get_gic_offset()
364 *gicc_base = NXP_GICC_64K_ADDR; in get_gic_offset()
368 *gicc_base = NXP_GICC_4K_ADDR; in get_gic_offset()
385 static uint32_t gicc_base, gicd_base; in soc_platform_setup() local
387 get_gic_offset(&gicc_base, &gicd_base); in soc_platform_setup()
388 plat_ls_gic_driver_init(gicd_base, gicc_base, in soc_platform_setup()
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| /arm-trusted-firmware-2.8.0/plat/qemu/common/ |
| A D | qemu_gicv2.c | 18 .gicc_base = GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/ |
| A D | rockchip_gicv2.c | 38 .gicc_base = PLAT_RK_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/ |
| A D | poplar_gicv2.c | 25 .gicc_base = POPLAR_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/ |
| A D | tegra_gicv2.c | 36 tegra_gic_data.gicc_base = TEGRA_GICC_BASE; in tegra_gic_setup()
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| /arm-trusted-firmware-2.8.0/drivers/nxp/gic/ |
| A D | ls_gicv2.c | 25 ls_gic_data.gicc_base = nxp_gicc_addr; in plat_ls_gic_driver_init()
|
| /arm-trusted-firmware-2.8.0/plat/arm/common/ |
| A D | arm_gicv2.c | 36 .gicc_base = PLAT_ARM_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/gic/gicv2/ |
| A D | plat_gic.h | 69 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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| /arm-trusted-firmware-2.8.0/plat/qti/msm8916/ |
| A D | msm8916_gicv2.c | 48 .gicc_base = APCS_QGIC2_GICC,
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| /arm-trusted-firmware-2.8.0/plat/st/stm32mp1/ |
| A D | stm32mp1_gic.c | 67 platform_gic_data.gicc_base = fdt32_to_cpu(*(cuint + 2)); in stm32mp1_gic_init()
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| /arm-trusted-firmware-2.8.0/plat/marvell/armada/common/ |
| A D | marvell_gicv2.c | 59 .gicc_base = PLAT_MARVELL_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/amlogic/gxbb/ |
| A D | gxbb_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey/ |
| A D | hikey_bl31_setup.c | 50 .gicc_base = PLAT_ARM_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/allwinner/common/ |
| A D | sunxi_bl31_setup.c | 39 .gicc_base = SUNXI_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/qemu/common/sp_min/ |
| A D | sp_min_setup.c | 63 .gicc_base = GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/amlogic/g12a/ |
| A D | g12a_bl31_setup.c | 129 .gicc_base = AML_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/amlogic/gxl/ |
| A D | gxl_bl31_setup.c | 145 .gicc_base = AML_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/amlogic/axg/ |
| A D | axg_bl31_setup.c | 155 .gicc_base = AML_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/agilex/ |
| A D | bl31_plat_setup.c | 93 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/include/drivers/arm/ |
| A D | gicv2.h | 164 uintptr_t gicc_base; member
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/n5x/ |
| A D | bl31_plat_setup.c | 94 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/intel/soc/stratix10/ |
| A D | bl31_plat_setup.c | 101 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/rpi/rpi4/ |
| A D | rpi4_bl31_setup.c | 41 .gicc_base = RPI4_GIC_GICC_BASE,
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/hikey960/ |
| A D | hikey960_bl31_setup.c | 52 .gicc_base = GICC_REG_BASE,
|