| /arm-trusted-firmware-2.8.0/drivers/arm/gic/v2/ |
| A D | gicv2_helpers.c | 96 num_ints = gicd_read_typer(gicd_base); in gicv2_spis_configure_defaults()
105 gicd_write_igroupr(gicd_base, index, ~0U); in gicv2_spis_configure_defaults()
109 gicd_write_ipriorityr(gicd_base, in gicv2_spis_configure_defaults()
115 gicd_write_icfgr(gicd_base, index, 0U); in gicv2_spis_configure_defaults()
140 gicd_clr_igroupr(gicd_base, prop_desc->intr_num); in gicv2_secure_spis_configure_props()
143 gicd_set_ipriorityr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
147 gicd_set_itargetsr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
148 gicv2_get_cpuif_id(gicd_base)); in gicv2_secure_spis_configure_props()
151 gicd_set_icfgr(gicd_base, prop_desc->intr_num, in gicv2_secure_spis_configure_props()
179 gicd_write_icenabler(gicd_base, 0U, ~0U); in gicv2_secure_ppi_sgi_setup_props()
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| A D | gicv2_main.c | 82 assert(driver_data->gicd_base != 0U); in gicv2_pcpu_distif_init()
91 gicd_write_ctlr(driver_data->gicd_base, in gicv2_pcpu_distif_init()
106 assert(driver_data->gicd_base != 0U); in gicv2_distif_init()
110 gicd_write_ctlr(driver_data->gicd_base, in gicv2_distif_init()
272 assert(driver_data->gicd_base != 0U); in gicv2_get_interrupt_group()
298 assert(driver_data->gicd_base != 0U); in gicv2_set_pe_target_mask()
336 assert(driver_data->gicd_base != 0U); in gicv2_get_interrupt_active()
348 assert(driver_data->gicd_base != 0U); in gicv2_enable_interrupt()
365 assert(driver_data->gicd_base != 0U); in gicv2_disable_interrupt()
383 assert(driver_data->gicd_base != 0U); in gicv2_set_interrupt_priority()
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| A D | gicv2_private.h | 18 void gicv2_spis_configure_defaults(uintptr_t gicd_base);
19 void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
22 void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
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| /arm-trusted-firmware-2.8.0/drivers/arm/gic/v3/ |
| A D | gicv3_main.c | 103 assert(plat_driver_data->gicd_base != 0U); in gicv3_driver_init()
188 assert(gicv3_driver_data->gicd_base != 0U); in gicv3_distif_init()
197 gicd_clr_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
204 gicd_set_ctlr(gicv3_driver_data->gicd_base, in gicv3_distif_init()
211 gicv3_driver_data->gicd_base, in gicv3_distif_init()
233 assert(gicv3_driver_data->gicd_base != 0U); in gicv3_rdistif_init()
744 uintptr_t gicd_base = gicv3_driver_data->gicd_base; in gicv3_distif_save() local
751 gicd_wait_for_pending_write(gicd_base); in gicv3_distif_save()
831 uintptr_t gicd_base = gicv3_driver_data->gicd_base; in gicv3_distif_init_restore() local
838 gicd_clr_ctlr(gicd_base, in gicv3_distif_init_restore()
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| A D | gicv3_helpers.c | 151 gicd_write_igroupr(gicd_base, i, ~0U); in gicv3_spis_config_defaults()
161 gicd_write_igroupr(gicd_base, i, ~0U); in gicv3_spis_config_defaults()
183 gicd_write_icfgr(gicd_base, i, 0U); in gicv3_spis_config_defaults()
188 gicd_write_icfgr(gicd_base, i, 0U); in gicv3_spis_config_defaults()
221 gicd_clr_igroupr(gicd_base, intr_num); in gicv3_secure_spis_config_props()
228 gicd_set_igrpmodr(gicd_base, intr_num); in gicv3_secure_spis_config_props()
231 gicd_clr_igrpmodr(gicd_base, intr_num); in gicv3_secure_spis_config_props()
239 gicd_set_ipriorityr(gicd_base, intr_num, in gicv3_secure_spis_config_props()
245 gicd_write_irouter(gicd_base, intr_num, in gicv3_secure_spis_config_props()
249 gicd_set_isenabler(gicd_base, intr_num); in gicv3_secure_spis_config_props()
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| A D | gic-x00.c | 197 void gicv3_check_erratas_applies(uintptr_t gicd_base) in gicv3_check_erratas_applies() argument
202 assert(gicd_base != 0UL); in gicv3_check_erratas_applies()
204 gicv3_get_component_prodid_rev(gicd_base, &gic_prod_id, &gic_rev); in gicv3_check_erratas_applies()
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| /arm-trusted-firmware-2.8.0/plat/nxp/soc-ls1043a/ |
| A D | soc.c | 349 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base) in get_gic_offset() argument
362 *gicd_base = NXP_GICD_4K_ADDR; in get_gic_offset()
365 *gicd_base = NXP_GICD_64K_ADDR; in get_gic_offset()
369 *gicd_base = NXP_GICD_4K_ADDR; in get_gic_offset()
385 static uint32_t gicc_base, gicd_base; in soc_platform_setup() local
387 get_gic_offset(&gicc_base, &gicd_base); in soc_platform_setup()
388 plat_ls_gic_driver_init(gicd_base, gicc_base, in soc_platform_setup()
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| /arm-trusted-firmware-2.8.0/plat/ti/k3/common/ |
| A D | k3_gicv3.c | 48 uintptr_t gicd_base = gic_base; in k3_gic_driver_init() local
70 k3_gic_data.gicd_base = gicd_base; in k3_gic_driver_init()
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| /arm-trusted-firmware-2.8.0/plat/socionext/uniphier/ |
| A D | uniphier_gicv3.c | 61 .gicd_base = 0x5fe00000,
70 .gicd_base = 0x5fe00000,
79 .gicd_base = 0x5fe00000,
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| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/ |
| A D | fvp_gicv3.c | 109 fvp_gic_data.gicd_base = (uintptr_t)FCONF_GET_PROPERTY(hw_config, in plat_arm_gic_driver_init()
111 gicd_base); in plat_arm_gic_driver_init()
124 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; in plat_arm_gic_driver_init()
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| /arm-trusted-firmware-2.8.0/plat/arm/board/arm_fpga/ |
| A D | fpga_gicv3.c | 55 &fpga_gicv3_driver_data.gicd_base, NULL); in plat_fpga_gic_init()
61 iidr = mmio_read_32(fpga_gicv3_driver_data.gicd_base + GICD_IIDR); in plat_fpga_gic_init()
71 gicr_base = fpga_gicv3_driver_data.gicd_base + (4U << 16); in plat_fpga_gic_init()
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| /arm-trusted-firmware-2.8.0/plat/qemu/common/ |
| A D | qemu_gicv2.c | 17 .gicd_base = GICD_BASE,
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| A D | qemu_gicv3.c | 25 .gicd_base = GICD_BASE,
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| /arm-trusted-firmware-2.8.0/plat/rockchip/common/ |
| A D | rockchip_gicv2.c | 37 .gicd_base = PLAT_RK_GICD_BASE,
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| A D | rockchip_gicv3.c | 39 .gicd_base = PLAT_RK_GICD_BASE,
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| /arm-trusted-firmware-2.8.0/plat/hisilicon/poplar/ |
| A D | poplar_gicv2.c | 24 .gicd_base = POPLAR_GICD_BASE,
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| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/ |
| A D | tegra_gicv2.c | 35 tegra_gic_data.gicd_base = TEGRA_GICD_BASE; in tegra_gic_setup()
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| A D | tegra_gicv3.c | 40 tegra_gic_data.gicd_base = TEGRA_GICD_BASE; in tegra_gic_setup()
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| /arm-trusted-firmware-2.8.0/drivers/nxp/gic/ |
| A D | ls_gicv2.c | 24 ls_gic_data.gicd_base = nxp_gicd_addr; in plat_ls_gic_driver_init()
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| A D | ls_gicv3.c | 25 ls_gic_data.gicd_base = nxp_gicd_addr; in plat_ls_gic_driver_init()
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| /arm-trusted-firmware-2.8.0/plat/arm/common/ |
| A D | arm_gicv2.c | 35 .gicd_base = PLAT_ARM_GICD_BASE,
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| /arm-trusted-firmware-2.8.0/plat/brcm/common/ |
| A D | brcm_gicv3.c | 43 .gicd_base = PLAT_BRCM_GICD_BASE,
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| /arm-trusted-firmware-2.8.0/include/drivers/nxp/gic/gicv2/ |
| A D | plat_gic.h | 69 void get_gic_offset(uint32_t *gicc_base, uint32_t *gicd_base);
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| /arm-trusted-firmware-2.8.0/plat/arm/board/fvp/include/ |
| A D | fconf_hw_config_getter.h | 19 uint64_t gicd_base; member
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| /arm-trusted-firmware-2.8.0/plat/qti/msm8916/ |
| A D | msm8916_gicv2.c | 47 .gicd_base = APCS_QGIC2_GICD,
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