Searched refs:gpregs_ctx (Results 1 – 3 of 3) sorted by relevance
| /arm-trusted-firmware-2.8.0/plat/nvidia/tegra/common/ |
| A D | tegra_fiq_glue.c | 130 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); in tegra_fiq_get_intr_context() local
139 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); in tegra_fiq_get_intr_context()
140 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); in tegra_fiq_get_intr_context()
142 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); in tegra_fiq_get_intr_context()
143 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); in tegra_fiq_get_intr_context()
146 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); in tegra_fiq_get_intr_context()
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| /arm-trusted-firmware-2.8.0/services/std_svc/spm/el3_spmc/ |
| A D | spmc_pm.c | 107 gp_regs_t *gpregs_ctx; in spmc_send_pm_msg() local
149 gpregs_ctx = get_gpregs_ctx(&ec->cpu_ctx); in spmc_send_pm_msg()
152 resp = read_ctx_reg(gpregs_ctx, CTX_GPREG_X0); in spmc_send_pm_msg()
160 resp = read_ctx_reg(gpregs_ctx, CTX_GPREG_X1); in spmc_send_pm_msg()
169 resp = read_ctx_reg(gpregs_ctx, CTX_GPREG_X2); in spmc_send_pm_msg()
181 return read_ctx_reg(gpregs_ctx, CTX_GPREG_X3); in spmc_send_pm_msg()
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| /arm-trusted-firmware-2.8.0/include/lib/el3_runtime/aarch64/ |
| A D | context.h | 413 gp_regs_t gpregs_ctx; member
437 #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
448 CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
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