| /arm-trusted-firmware-2.8.0/lib/zlib/ |
| A D | inflate.c | 512 have--; \
655 in = have;
766 if (copy > have) copy = have;
800 have -= copy;
922 if (copy > have) copy = have;
952 state->have = 0;
974 state->have = 0;
1405 unsigned FAR *have; in syncsearch()
1412 got = *have;
1423 *have = got;
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| A D | inflate.h | 118 unsigned have; /* number of code lengths in lens[] */ member
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| A D | zlib.h | 1835 unsigned have; member
1843 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
1846 ((g)->have ? ((g)->have--, (g)->pos++, *((g)->next)++) : (gzgetc)(g))
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| /arm-trusted-firmware-2.8.0/ |
| A D | dco.txt | 18 have the right to submit it under the open source license
23 license and I have the right under that license to submit that
30 person who certified (a), (b) or (c) and I have not modified
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| /arm-trusted-firmware-2.8.0/docs/plat/ |
| A D | nvidia-tegra.rst | 25 including legacy ARMv7 applications. The Denver 2 processors each have 128 KB
26 Instruction and 64 KB Data Level 1 caches; and have a 2MB shared Level 2
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
28 Data Level 1 caches; and also have a 2 MB shared Level 2 unified cache. A
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
64 48 KB Instruction and 32 KB Data Level 1 caches; and have a 2 MB shared
65 Level 2 unified cache. The Cortex-A53 processors each have 32 KB Instruction
66 and 32 KB Data Level 1 caches; and have a 512 KB shared Level 2 unified cache.
100 the scatter file to be used. Tegra platforms have verified BL31 image generation
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| A D | rpi4.rst | 10 as well, but have not been tested at this point.
29 ``config.txt``. You should have AArch64 code in the file loaded as the
73 memory. The load addresses have a default, but can also be changed by
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| A D | index.rst | 55 currently have associated documentation:
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| A D | qti-msm8916.rst | 69 The `DragonBoard 410c`_ does not have secure boot enabled by default. In this
79 Do not flash incorrectly signed firmware on devices that have secure
80 boot enabled! Make sure that you have a way to recover the board in case
|
| A D | xilinx-zynqmp.rst | 19 To build bl32 TSP you have to rebuild bl31 too:
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| /arm-trusted-firmware-2.8.0/docs/design_documents/ |
| A D | context_mgmt_rework.rst | 23 It is expected that the suggestions below could have legacy implications and
35 Both the Secure and Realm worlds have associated dispatcher component in
43 The Non Secure world does not have a dispatcher component and hence EL3
44 firmware (BL31)/context management library needs to have routines to help
78 both Realm and Secure world will have the same feature set enabled from
86 FEAT_xxx build option. It is a valid configuration to have
108 have the library do only the common init needed. The library can export
122 Till now, we have been ignoring the fact that Root world (or EL3) itself could
123 have some settings which are distinct from NS/S/Realm worlds. In this case,
145 itself may have some settings to apply for various reasons. A good example for
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| A D | cmake_framework.rst | 96 generation or dtc for device tree compilation. These tools have to be found
108 In the provisioning phase, first we have to obtain the necessary resources, i.e.
109 clone the code repository and other dependencies. Next we have to do the
118 Usually during development only the steps in this second phase have to be
131 it. This means that all source and header files used by the target will have all
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| /arm-trusted-firmware-2.8.0/docs/threat_model/ |
| A D | index.rst | 8 using a data flow diagram. Then we provide a list of threats we have identified
|
| /arm-trusted-firmware-2.8.0/docs/design/ |
| A D | psci-pd-tree.rst | 54 ``plat_get_aff_count()`` and ``plat_get_aff_state()`` have been
59 where the power domain tree does not have a single root node, for example,
74 above text further. The leaf and non-leaf nodes in this tree have been numbered
132 platform API have changed since it is required to validate the passed MPIDR. It
156 contiguous or certain cores have been disabled. This essentially means that the
157 MPIDRs have been sparsely allocated, that is, the size of the range of MPIDRs
178 To fulfill requirement 3 and 4, separate data structures have been defined
200 * -> cpu_start_idx + ncpus' have this node as their parent.
243 node. Other fields have been ignored for simplicity.
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| /arm-trusted-firmware-2.8.0/docs/process/ |
| A D | code-review-guidelines.rst | 33 to different timescales, and have different priorities. Keep this in
65 - If there is only one code owner and they have become unresponsive, ask one
73 directory to have the freedom to change it in any way. This way, your changes
80 There are no good or bad review comments. If you have any doubt about a patch or
128 through the ``Code-Owner-Review+1`` label in Gerrit. If instead, they have
178 - New files must have the correct license and copyright headers. See :ref:`this
203 - Before merging a patch, verify that all review comments have been addressed.
208 through the ``Maintainer-Review+1`` label in Gerrit. If instead, they have
|
| A D | faq.rst | 24 they follow the coding guidelines, have already had some code review, and have
48 time. In simple cases where all potential regressions have already been tested,
|
| A D | security.rst | 24 If you think you have found a security vulnerability, please **do not**
29 TF-A have a chance to consider the implications of the vulnerability and its
|
| A D | commit-style.rst | 18 - What impact does it have?
101 does not yet have a designated scope, please add one.
138 Ensure that each commit also has a unique ``Change-Id:`` line. If you have
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| /arm-trusted-firmware-2.8.0/docs/about/ |
| A D | contact.rst | 8 If you think you have found a security vulnerability, please report this using
46 Arm licensees have an additional support conduit - they may contact Arm directly
|
| /arm-trusted-firmware-2.8.0/fdts/ |
| A D | juno-ethosn.dtsi | 8 * This device tree is only an example and some properties have been omitted.
|
| /arm-trusted-firmware-2.8.0/docs/plat/marvell/armada/misc/ |
| A D | mvebu-io-win.rst | 8 Transactions that are decoded by CCU windows as IO peripheral, have an additional
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| /arm-trusted-firmware-2.8.0/docs/getting_started/ |
| A D | docs-build.rst | 9 check that you have the required software packages, as described in the
28 argument will install them locally, but you have to add their location to
|
| A D | prerequisites.rst | 17 have performed tests using Ubuntu 20.04 LTS (64-bit) but other distributions
153 If you have Node.js installed already, you can automatically install this hook,
161 If you have opted **not** to install Node.js, you can install the Gerrit hook
|
| A D | image-terminology.rst | 10 - Some of the names and abbreviated names have changed to accommodate new
95 have additional images and/or a different load/execution ordering. The
141 The terminology for these images has not been widely adopted yet but they have
181 Some systems may have additional processors to the AP and SCP. For example, a
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| /arm-trusted-firmware-2.8.0/docs/ |
| A D | index.rst | 76 have additional documentation that has been provided by the maintainers of the
83 have previously been raised against the software.
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| /arm-trusted-firmware-2.8.0/docs/security_advisories/ |
| A D | security-advisory-tfv-7.rst | 37 (SDEI)`_. Also, the TF-A project does not have visibility of all
45 have a system performance impact, which varies for each CPU type and use-case.
|